Francis N Nguyen
Examiner (ID: 14942)
Most Active Art Unit | 2674 |
Art Unit(s) | 2774, 2674 |
Total Applications | 207 |
Issued Applications | 164 |
Pending Applications | 29 |
Abandoned Applications | 14 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1014590
[patent_doc_number] => 06893932
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-17
[patent_title] => 'Heterojunction bipolar transistor containing at least one silicon carbide layer'
[patent_app_type] => utility
[patent_app_number] => 10/826120
[patent_app_country] => US
[patent_app_date] => 2004-04-15
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/893/06893932.pdf
[firstpage_image] =>[orig_patent_app_number] => 10826120
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/826120 | Heterojunction bipolar transistor containing at least one silicon carbide layer | Apr 14, 2004 | Issued |
Array
(
[id] => 7375389
[patent_doc_number] => 20040178446
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-16
[patent_title] => 'Method of forming asymmetrical polysilicon thin film transistor'
[patent_app_type] => new
[patent_app_number] => 10/811729
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[patent_app_date] => 2004-03-29
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[firstpage_image] =>[orig_patent_app_number] => 10811729
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/811729 | Method of forming asymmetrical polysilicon thin film transistor | Mar 28, 2004 | Abandoned |
Array
(
[id] => 1068719
[patent_doc_number] => 06844245
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-18
[patent_title] => 'Method of preparing a self-passivating Cu laser fuse'
[patent_app_type] => utility
[patent_app_number] => 10/745263
[patent_app_country] => US
[patent_app_date] => 2003-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[pdf_file] => patents/06/844/06844245.pdf
[firstpage_image] =>[orig_patent_app_number] => 10745263
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/745263 | Method of preparing a self-passivating Cu laser fuse | Dec 22, 2003 | Issued |
Array
(
[id] => 1047374
[patent_doc_number] => 06864561
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-08
[patent_title] => 'Method and apparatus for reducing fixed charge in semiconductor device layers'
[patent_app_type] => utility
[patent_app_number] => 10/727889
[patent_app_country] => US
[patent_app_date] => 2003-12-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/864/06864561.pdf
[firstpage_image] =>[orig_patent_app_number] => 10727889
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/727889 | Method and apparatus for reducing fixed charge in semiconductor device layers | Dec 3, 2003 | Issued |
Array
(
[id] => 7466835
[patent_doc_number] => 20040102016
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[patent_issue_date] => 2004-05-27
[patent_title] => 'Method for forming an isolation region in a semiconductor device'
[patent_app_type] => new
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[patent_app_country] => US
[patent_app_date] => 2003-10-10
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[firstpage_image] =>[orig_patent_app_number] => 10682031
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/682031 | Method for forming an isolation region in a semiconductor device | Oct 9, 2003 | Abandoned |
Array
(
[id] => 999852
[patent_doc_number] => 06911703
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-28
[patent_title] => 'Semiconductor integrated circuit device operating with low power consumption'
[patent_app_type] => utility
[patent_app_number] => 10/680397
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[pdf_file] => patents/06/911/06911703.pdf
[firstpage_image] =>[orig_patent_app_number] => 10680397
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/680397 | Semiconductor integrated circuit device operating with low power consumption | Oct 7, 2003 | Issued |
Array
(
[id] => 991070
[patent_doc_number] => 06919597
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-19
[patent_title] => 'Bismuth titanium silicon oxide, bismuth titanium silicon oxide thin film, and method for forming the thin film'
[patent_app_type] => utility
[patent_app_number] => 10/634841
[patent_app_country] => US
[patent_app_date] => 2003-08-06
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[pdf_file] => patents/06/919/06919597.pdf
[firstpage_image] =>[orig_patent_app_number] => 10634841
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/634841 | Bismuth titanium silicon oxide, bismuth titanium silicon oxide thin film, and method for forming the thin film | Aug 5, 2003 | Issued |
Array
(
[id] => 7120351
[patent_doc_number] => 20050012180
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'BIPOLAR TRANSISTOR SELF-ALIGNMENT WITH RAISED EXTRINSIC BASE EXTENSION AND METHODS OF FORMING SAME'
[patent_app_type] => utility
[patent_app_number] => 10/604212
[patent_app_country] => US
[patent_app_date] => 2003-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[patent_no_of_words] => 4930
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[pdf_file] => publications/A1/0012/20050012180.pdf
[firstpage_image] =>[orig_patent_app_number] => 10604212
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604212 | Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same | Jun 30, 2003 | Issued |
Array
(
[id] => 972137
[patent_doc_number] => 06936522
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-30
[patent_title] => 'Selective silicon-on-insulator isolation structure and method'
[patent_app_type] => utility
[patent_app_number] => 10/604102
[patent_app_country] => US
[patent_app_date] => 2003-06-26
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[pdf_file] => patents/06/936/06936522.pdf
[firstpage_image] =>[orig_patent_app_number] => 10604102
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604102 | Selective silicon-on-insulator isolation structure and method | Jun 25, 2003 | Issued |
Array
(
[id] => 6662183
[patent_doc_number] => 20030201509
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-30
[patent_title] => 'Pinned floating photoreceptor with active pixel sensor'
[patent_app_type] => new
[patent_app_number] => 10/443839
[patent_app_country] => US
[patent_app_date] => 2003-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[firstpage_image] =>[orig_patent_app_number] => 10443839
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/443839 | Pinned floating photoreceptor with active pixel sensor | May 22, 2003 | Issued |
Array
(
[id] => 7448110
[patent_doc_number] => 20040164354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-26
[patent_title] => 'Minimum-dimension,\n fully- silicided MOS driver and ESD protection design for optimized inter-finger coupling'
[patent_app_type] => new
[patent_app_number] => 10/435817
[patent_app_country] => US
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[pdf_file] => publications/A1/0164/20040164354.pdf
[firstpage_image] =>[orig_patent_app_number] => 10435817
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/435817 | Minimum-dimension, fully-silicided MOS driver and ESD protection design for optimized inter-finger coupling | May 11, 2003 | Issued |
Array
(
[id] => 7291791
[patent_doc_number] => 20040212048
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Semiconductor structures, and methods of forming rugged semiconductor-containing surfaces'
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[patent_app_country] => US
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[pdf_file] => publications/A1/0212/20040212048.pdf
[firstpage_image] =>[orig_patent_app_number] => 10423111
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/423111 | Methods of forming rugged semiconductor-containing surfaces | Apr 24, 2003 | Issued |
Array
(
[id] => 972656
[patent_doc_number] => 06936905
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-30
[patent_title] => 'Two mask shottky diode with locos structure'
[patent_app_type] => utility
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10421781
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/421781 | Two mask shottky diode with locos structure | Apr 23, 2003 | Issued |
Array
(
[id] => 7612455
[patent_doc_number] => 06903381
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-07
[patent_title] => 'Light-emitting diode with cavity containing a filler'
[patent_app_type] => utility
[patent_app_number] => 10/421742
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10421742
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/421742 | Light-emitting diode with cavity containing a filler | Apr 23, 2003 | Issued |
Array
(
[id] => 7447667
[patent_doc_number] => 20040164313
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-26
[patent_title] => 'Trench capacitor with buried strap'
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[patent_app_number] => 10/248801
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[firstpage_image] =>[orig_patent_app_number] => 10248801
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/248801 | Trench capacitor with buried strap | Feb 19, 2003 | Issued |
10/367018 | Semiconductor device comprising capacitor and method of fabricating the same | Feb 13, 2003 | Abandoned |
Array
(
[id] => 1015023
[patent_doc_number] => 06894367
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-17
[patent_title] => 'Vertical bipolar transistor'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 10367005
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/367005 | Vertical bipolar transistor | Feb 13, 2003 | Issued |
Array
(
[id] => 1024529
[patent_doc_number] => 06884674
[patent_country] => US
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[patent_issue_date] => 2005-04-26
[patent_title] => 'Method for fabricating a semiconductor device including a capacitance insulating film having a perovskite structure'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/365502 | Method for fabricating a semiconductor device including a capacitance insulating film having a perovskite structure | Feb 12, 2003 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/361377 | High-voltage lateral transistor with a multi-layered extended drain structure | Feb 9, 2003 | Issued |
Array
(
[id] => 1080471
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[patent_issue_date] => 2004-12-28
[patent_title] => 'Power integrated circuit with vertical current flow and related manufacturing process'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/350403 | Power integrated circuit with vertical current flow and related manufacturing process | Jan 22, 2003 | Issued |