Search

Francisco Javier Aponte

Examiner (ID: 2180, Phone: (571)270-7164 , Office: P/2199 )

Most Active Art Unit
2199
Art Unit(s)
2198, 2151, 2199, 2158
Total Applications
690
Issued Applications
583
Pending Applications
65
Abandoned Applications
76

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11452024 [patent_doc_number] => 09575666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Efficient register preservation on processors' [patent_app_type] => utility [patent_app_number] => 14/824298 [patent_app_country] => US [patent_app_date] => 2015-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5064 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14824298 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/824298
Efficient register preservation on processors Aug 11, 2015 Issued
Array ( [id] => 11423691 [patent_doc_number] => 20170031835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'ADDRESS CACHING IN SWITCHES' [patent_app_type] => utility [patent_app_number] => 14/810062 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10153 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810062 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/810062
Address caching in switches Jul 26, 2015 Issued
Array ( [id] => 10695760 [patent_doc_number] => 20160041907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'SYSTEMS AND METHODS TO MANAGE TIERED CACHE DATA STORAGE' [patent_app_type] => utility [patent_app_number] => 14/810366 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10375 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810366 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/810366
Systems and methods to manage tiered cache data storage Jul 26, 2015 Issued
Array ( [id] => 12194669 [patent_doc_number] => 09898399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Memory management apparatus and method' [patent_app_type] => utility [patent_app_number] => 14/791856 [patent_app_country] => US [patent_app_date] => 2015-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6759 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14791856 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/791856
Memory management apparatus and method Jul 5, 2015 Issued
Array ( [id] => 12950284 [patent_doc_number] => 09836220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Data processing system and method of operating the same [patent_app_type] => utility [patent_app_number] => 14/791714 [patent_app_country] => US [patent_app_date] => 2015-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 8301 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14791714 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/791714
Data processing system and method of operating the same Jul 5, 2015 Issued
Array ( [id] => 11365906 [patent_doc_number] => 20170003887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'SYSTEMS AND METHODS FOR PROVIDING NON-POWER-OF-TWO FLASH CELL MAPPING' [patent_app_type] => utility [patent_app_number] => 14/791340 [patent_app_country] => US [patent_app_date] => 2015-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7028 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14791340 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/791340
Systems and methods for providing non-power-of-two flash cell mapping Jul 2, 2015 Issued
Array ( [id] => 11875270 [patent_doc_number] => 09747040 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-29 [patent_title] => 'Method and system for machine learning for write command selection based on technology feedback' [patent_app_type] => utility [patent_app_number] => 14/755652 [patent_app_country] => US [patent_app_date] => 2015-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7235 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14755652 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/755652
Method and system for machine learning for write command selection based on technology feedback Jun 29, 2015 Issued
Array ( [id] => 10401569 [patent_doc_number] => 20150286578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'MEMORY AND PROCESS SHARING VIA INPUT/OUTPUT WITH VIRTUALIZATION' [patent_app_type] => utility [patent_app_number] => 14/742809 [patent_app_country] => US [patent_app_date] => 2015-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3205 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14742809 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/742809
MEMORY AND PROCESS SHARING VIA INPUT/OUTPUT WITH VIRTUALIZATION Jun 17, 2015 Abandoned
Array ( [id] => 11795848 [patent_doc_number] => 09405677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-02 [patent_title] => 'Dynamic tuning of internal parameters for solid-state disk based on workload access patterns' [patent_app_type] => utility [patent_app_number] => 14/742395 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14742395 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/742395
Dynamic tuning of internal parameters for solid-state disk based on workload access patterns Jun 16, 2015 Issued
Array ( [id] => 11338410 [patent_doc_number] => 20160364165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'REDUCING NEW EXTENT FAILURES ON TARGET DEVICE DURING NON-DISRUPTIVE LOGICAL DATA SET MIGRATION' [patent_app_type] => utility [patent_app_number] => 14/735356 [patent_app_country] => US [patent_app_date] => 2015-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12176 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14735356 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/735356
Reducing new extent failures on target device during non-disruptive logical data set migration Jun 9, 2015 Issued
Array ( [id] => 10991279 [patent_doc_number] => 20160188224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'COMPUTING SYSTEM WITH BUFFER AND METHOD OF OPERATION THEREOF' [patent_app_type] => utility [patent_app_number] => 14/735765 [patent_app_country] => US [patent_app_date] => 2015-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6706 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14735765 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/735765
Computing system with write buffer including speculative storage write and method of operation thereof Jun 9, 2015 Issued
Array ( [id] => 11724279 [patent_doc_number] => 09697134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Memory having a static cache and a dynamic cache' [patent_app_type] => utility [patent_app_number] => 14/735498 [patent_app_country] => US [patent_app_date] => 2015-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5871 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14735498 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/735498
Memory having a static cache and a dynamic cache Jun 9, 2015 Issued
Array ( [id] => 10478104 [patent_doc_number] => 20150363121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'INTERFACE FOR CONNECTING HARDWARE COMPONENTS' [patent_app_type] => utility [patent_app_number] => 14/735274 [patent_app_country] => US [patent_app_date] => 2015-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 19610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14735274 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/735274
Receptacles for memory devices and methods of operation thereof Jun 9, 2015 Issued
Array ( [id] => 11306647 [patent_doc_number] => 09514046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-06 [patent_title] => 'Dynamic detection and software correction of incorrect lock and atomic update hint bits' [patent_app_type] => utility [patent_app_number] => 14/735429 [patent_app_country] => US [patent_app_date] => 2015-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3796 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14735429 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/735429
Dynamic detection and software correction of incorrect lock and atomic update hint bits Jun 9, 2015 Issued
Array ( [id] => 11830501 [patent_doc_number] => 09727242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Selective memory dump using usertokens' [patent_app_type] => utility [patent_app_number] => 14/735194 [patent_app_country] => US [patent_app_date] => 2015-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14735194 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/735194
Selective memory dump using usertokens Jun 9, 2015 Issued
Array ( [id] => 11830498 [patent_doc_number] => 09727239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Electronic system with partitioning mechanism and method of operation thereof' [patent_app_type] => utility [patent_app_number] => 14/725712 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14725712 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/725712
Electronic system with partitioning mechanism and method of operation thereof May 28, 2015 Issued
Array ( [id] => 10462004 [patent_doc_number] => 20150347019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'SYSTEMS AND METHODS FOR SEGMENTING DATA STRUCTURES IN A MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/726150 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14726150 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/726150
Systems and methods for segmenting data structures in a memory system May 28, 2015 Issued
Array ( [id] => 10376662 [patent_doc_number] => 20150261668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'Semiconductor Device and Method of Controlling Non-Volatile Memory Device' [patent_app_type] => utility [patent_app_number] => 14/725273 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 16835 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14725273 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/725273
Semiconductor device and method of controlling non-volatile memory device May 28, 2015 Issued
Array ( [id] => 11306645 [patent_doc_number] => 09514043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-06 [patent_title] => 'Systems and methods for utilizing wear leveling windows with non-volatile memory systems' [patent_app_type] => utility [patent_app_number] => 14/710135 [patent_app_country] => US [patent_app_date] => 2015-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9052 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14710135 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/710135
Systems and methods for utilizing wear leveling windows with non-volatile memory systems May 11, 2015 Issued
Array ( [id] => 12167649 [patent_doc_number] => 09886418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-06 [patent_title] => 'Matrix operands for linear algebra operations' [patent_app_type] => utility [patent_app_number] => 14/697728 [patent_app_country] => US [patent_app_date] => 2015-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5612 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14697728 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/697728
Matrix operands for linear algebra operations Apr 27, 2015 Issued
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