Search

Francisco Javier Aponte

Examiner (ID: 2180, Phone: (571)270-7164 , Office: P/2199 )

Most Active Art Unit
2199
Art Unit(s)
2198, 2151, 2199, 2158
Total Applications
690
Issued Applications
583
Pending Applications
65
Abandoned Applications
76

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11307386 [patent_doc_number] => 09514789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Systems and methods for safely moving short term memory devices while preserving, protecting and examining their digital data' [patent_app_type] => utility [patent_app_number] => 14/311337 [patent_app_country] => US [patent_app_date] => 2014-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5171 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14311337 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/311337
Systems and methods for safely moving short term memory devices while preserving, protecting and examining their digital data Jun 21, 2014 Issued
Array ( [id] => 11665255 [patent_doc_number] => 20170153974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'DUAL SPACE STORAGE MANAGEMENT SYSTEM AND DATA READ/WRITE METHOD' [patent_app_type] => utility [patent_app_number] => 15/116882 [patent_app_country] => US [patent_app_date] => 2014-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13964 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15116882 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/116882
Dual space storage management system and data read/write method Jun 18, 2014 Issued
Array ( [id] => 9891535 [patent_doc_number] => 08977808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Mapping between program states and data patterns' [patent_app_type] => utility [patent_app_number] => 14/304420 [patent_app_country] => US [patent_app_date] => 2014-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 11926 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14304420 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/304420
Mapping between program states and data patterns Jun 12, 2014 Issued
Array ( [id] => 10589632 [patent_doc_number] => 09311249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer' [patent_app_type] => utility [patent_app_number] => 14/297605 [patent_app_country] => US [patent_app_date] => 2014-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 21507 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14297605 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/297605
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer Jun 4, 2014 Issued
Array ( [id] => 10609989 [patent_doc_number] => 09330023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces' [patent_app_type] => utility [patent_app_number] => 14/297326 [patent_app_country] => US [patent_app_date] => 2014-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 21527 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14297326 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/297326
Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces Jun 4, 2014 Issued
Array ( [id] => 9947510 [patent_doc_number] => 08996838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-31 [patent_title] => 'Structure variation detection for a memory having a three-dimensional memory configuration' [patent_app_type] => utility [patent_app_number] => 14/273031 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 22567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273031 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273031
Structure variation detection for a memory having a three-dimensional memory configuration May 7, 2014 Issued
Array ( [id] => 9673307 [patent_doc_number] => 20140237170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'STORAGE DEVICE, AND READ COMMAND EXECUTING METHOD' [patent_app_type] => utility [patent_app_number] => 14/264938 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6570 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14264938 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/264938
STORAGE DEVICE, AND READ COMMAND EXECUTING METHOD Apr 28, 2014 Abandoned
Array ( [id] => 10616490 [patent_doc_number] => 09335934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Shared memory controller and method of using same' [patent_app_type] => utility [patent_app_number] => 14/265127 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3699 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14265127 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/265127
Shared memory controller and method of using same Apr 28, 2014 Issued
Array ( [id] => 11258411 [patent_doc_number] => 09483310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Associating cache memory with a work process' [patent_app_type] => utility [patent_app_number] => 14/264812 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14264812 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/264812
Associating cache memory with a work process Apr 28, 2014 Issued
Array ( [id] => 10424724 [patent_doc_number] => 20150309735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'TECHNIQUES FOR REDUCING READ I/O LATENCY IN VIRTUAL MACHINES' [patent_app_type] => utility [patent_app_number] => 14/265036 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7220 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14265036 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/265036
Techniques for reducing read I/O latency in virtual machines Apr 28, 2014 Issued
Array ( [id] => 10623306 [patent_doc_number] => 09342248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Techniques for reducing read I/O latency in virtual machines' [patent_app_type] => utility [patent_app_number] => 14/265062 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7218 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14265062 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/265062
Techniques for reducing read I/O latency in virtual machines Apr 28, 2014 Issued
Array ( [id] => 9673318 [patent_doc_number] => 20140237181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'METHOD AND APPARATUS FOR PREPARING A CACHE REPLACEMENT CATALOG' [patent_app_type] => utility [patent_app_number] => 14/262357 [patent_app_country] => US [patent_app_date] => 2014-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14262357 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/262357
Method and apparatus for preparing a cache replacement catalog Apr 24, 2014 Issued
Array ( [id] => 10841185 [patent_doc_number] => 08868884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Method and apparatus for servicing read and write requests using a cache replacement catalog' [patent_app_type] => utility [patent_app_number] => 14/262366 [patent_app_country] => US [patent_app_date] => 2014-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6456 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14262366 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/262366
Method and apparatus for servicing read and write requests using a cache replacement catalog Apr 24, 2014 Issued
Array ( [id] => 9673320 [patent_doc_number] => 20140237183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'SYSTEMS AND METHODS FOR INTELLIGENT CONTENT AWARE CACHING' [patent_app_type] => utility [patent_app_number] => 14/262380 [patent_app_country] => US [patent_app_date] => 2014-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6435 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14262380 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/262380
Systems and methods for intelligent content aware caching Apr 24, 2014 Issued
Array ( [id] => 10922247 [patent_doc_number] => 20140325267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'SYSTEM AND METHOD FOR HIGH PERFORMANCE ENTERPRISE DATA PROTECTION' [patent_app_type] => utility [patent_app_number] => 14/256993 [patent_app_country] => US [patent_app_date] => 2014-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13232 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14256993 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/256993
System and method for high performance enterprise data protection Apr 20, 2014 Issued
Array ( [id] => 10242919 [patent_doc_number] => 20150127914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/255441 [patent_app_country] => US [patent_app_date] => 2014-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8271 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255441 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/255441
Semiconductor memory device, memory system and method of operating the same Apr 16, 2014 Issued
Array ( [id] => 10603127 [patent_doc_number] => 09323692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer' [patent_app_type] => utility [patent_app_number] => 14/255367 [patent_app_country] => US [patent_app_date] => 2014-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 21703 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255367 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/255367
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer Apr 16, 2014 Issued
Array ( [id] => 10416941 [patent_doc_number] => 20150301951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'MANAGING TRANSLATIONS ACROSS MULTIPLE CONTEXTS USING A TLB WITH ENTRIES DIRECTED TO MULTIPLE PRIVILEGE LEVELS AND TO MULTIPLE TYPES OF ADDRESS SPACES' [patent_app_type] => utility [patent_app_number] => 14/255457 [patent_app_country] => US [patent_app_date] => 2014-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 21913 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255457 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/255457
Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces Apr 16, 2014 Issued
Array ( [id] => 9658678 [patent_doc_number] => 20140229683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'SELF-DISABLING WORKING SET CACHE' [patent_app_type] => utility [patent_app_number] => 14/253856 [patent_app_country] => US [patent_app_date] => 2014-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14253856 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/253856
Self-disabling working set cache Apr 14, 2014 Issued
Array ( [id] => 10922103 [patent_doc_number] => 20140325124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'MEMORY SYSTEM AND METHOD FOR OPERATING A MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/248377 [patent_app_country] => US [patent_app_date] => 2014-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6057 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14248377 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/248377
Memory architecture for storing data in a plurality of memory chips Apr 8, 2014 Issued
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