Search

Francisco Javier Aponte

Examiner (ID: 2180, Phone: (571)270-7164 , Office: P/2199 )

Most Active Art Unit
2199
Art Unit(s)
2198, 2151, 2199, 2158
Total Applications
690
Issued Applications
583
Pending Applications
65
Abandoned Applications
76

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10099682 [patent_doc_number] => 09135997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'System and method for filtering addresses' [patent_app_type] => utility [patent_app_number] => 13/925331 [patent_app_country] => US [patent_app_date] => 2013-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925331 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/925331
System and method for filtering addresses Jun 23, 2013 Issued
Array ( [id] => 10015260 [patent_doc_number] => 09058274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'System and method of selective READ cache retention for a rebooted node of a multiple-node storage cluster' [patent_app_type] => utility [patent_app_number] => 13/924773 [patent_app_country] => US [patent_app_date] => 2013-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13924773 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/924773
System and method of selective READ cache retention for a rebooted node of a multiple-node storage cluster Jun 23, 2013 Issued
Array ( [id] => 9150451 [patent_doc_number] => 20130304974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'SYSTEM AND METHOD FOR STORING DATA USING A FLEXIBLE DATA FORMAT' [patent_app_type] => utility [patent_app_number] => 13/925789 [patent_app_country] => US [patent_app_date] => 2013-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925789 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/925789
SYSTEM AND METHOD FOR STORING DATA USING A FLEXIBLE DATA FORMAT Jun 23, 2013 Abandoned
Array ( [id] => 10928012 [patent_doc_number] => 20140331033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'FIRMWARE CODE LOADING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/925816 [patent_app_country] => US [patent_app_date] => 2013-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8850 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925816 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/925816
Firmware code loading method, memory controller and memory storage apparatus Jun 23, 2013 Issued
Array ( [id] => 10157607 [patent_doc_number] => 09189387 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-17 [patent_title] => 'Combined memory and storage tiering' [patent_app_type] => utility [patent_app_number] => 13/925143 [patent_app_country] => US [patent_app_date] => 2013-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925143 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/925143
Combined memory and storage tiering Jun 23, 2013 Issued
Array ( [id] => 9444133 [patent_doc_number] => 08713264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Data processing circuit with arbitration between a plurality of queues' [patent_app_type] => utility [patent_app_number] => 13/906224 [patent_app_country] => US [patent_app_date] => 2013-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7760 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13906224 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/906224
Data processing circuit with arbitration between a plurality of queues May 29, 2013 Issued
Array ( [id] => 9707265 [patent_doc_number] => 08832360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Solid state storage device controller with expansion mode' [patent_app_type] => utility [patent_app_number] => 13/901806 [patent_app_country] => US [patent_app_date] => 2013-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4675 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13901806 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/901806
Solid state storage device controller with expansion mode May 23, 2013 Issued
Array ( [id] => 10941523 [patent_doc_number] => 20140344545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'PARALLEL ATOMIC INCREMENT' [patent_app_type] => utility [patent_app_number] => 13/896588 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5641 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13896588 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/896588
Parallel atomic increment May 16, 2013 Issued
Array ( [id] => 9998919 [patent_doc_number] => 09043536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-26 [patent_title] => 'Method of recording mapping information, and memory controller and memory storage apparatus using the same' [patent_app_type] => utility [patent_app_number] => 13/896328 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 11114 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13896328 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/896328
Method of recording mapping information, and memory controller and memory storage apparatus using the same May 16, 2013 Issued
Array ( [id] => 9176326 [patent_doc_number] => 20130318311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'SYSTEM-ON-CHIP FOR PROVIDING ACCESS TO SHARED MEMORY VIA CHIP-TO-CHIP LINK, OPERATION METHOD OF THE SAME, AND ELECTRONIC SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/895606 [patent_app_country] => US [patent_app_date] => 2013-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895606 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/895606
System-on-chip for providing access to shared memory via chip-to-chip link, operation method of the same, and electronic system including the same May 15, 2013 Issued
Array ( [id] => 10941515 [patent_doc_number] => 20140344536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'STORAGE SYSTEMS THAT CREATE SNAPSHOT QUEUES' [patent_app_type] => utility [patent_app_number] => 13/895086 [patent_app_country] => US [patent_app_date] => 2013-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11050 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895086 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/895086
Storage systems that create snapshot queues May 14, 2013 Issued
Array ( [id] => 9056757 [patent_doc_number] => 20130254471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'DEVICE AND MEMORY SYSTEM FOR MEMORY MANAGEMENT USING ACCESS FREQUENCY INFORMATION' [patent_app_type] => utility [patent_app_number] => 13/890891 [patent_app_country] => US [patent_app_date] => 2013-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 13805 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13890891 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/890891
Device and memory system for swappable memory May 8, 2013 Issued
Array ( [id] => 10164187 [patent_doc_number] => 09195409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Storage system with load balancing mechanism and method of operation thereof' [patent_app_type] => utility [patent_app_number] => 13/872389 [patent_app_country] => US [patent_app_date] => 2013-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8411 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13872389 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/872389
Storage system with load balancing mechanism and method of operation thereof Apr 28, 2013 Issued
Array ( [id] => 10922121 [patent_doc_number] => 20140325142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'Input/Output De-Duplication Based on Variable-Size Chunks' [patent_app_type] => utility [patent_app_number] => 13/872444 [patent_app_country] => US [patent_app_date] => 2013-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5150 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13872444 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/872444
Input/output de-duplication based on variable-size chunks Apr 28, 2013 Issued
Array ( [id] => 10164238 [patent_doc_number] => 09195459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Simultaneously accessible memory device and method for using the same' [patent_app_type] => utility [patent_app_number] => 13/872014 [patent_app_country] => US [patent_app_date] => 2013-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 3057 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13872014 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/872014
Simultaneously accessible memory device and method for using the same Apr 25, 2013 Issued
Array ( [id] => 9203954 [patent_doc_number] => 20140003131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/860825 [patent_app_country] => US [patent_app_date] => 2013-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8429 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13860825 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/860825
Multi-column addressing mode memory system including an integrated circuit memory device Apr 10, 2013 Issued
Array ( [id] => 10680430 [patent_doc_number] => 20160026576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'IMPLEMENTING COHERENCY WITH REFLECTIVE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/763943 [patent_app_country] => US [patent_app_date] => 2013-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4681 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14763943 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/763943
Implementing coherency with reflective memory Mar 27, 2013 Issued
Array ( [id] => 10158350 [patent_doc_number] => 09190133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Apparatuses and methods for a memory die architecture including an interface memory' [patent_app_type] => utility [patent_app_number] => 13/793347 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4250 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13793347 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/793347
Apparatuses and methods for a memory die architecture including an interface memory Mar 10, 2013 Issued
Array ( [id] => 10009312 [patent_doc_number] => 09052833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Protection of former primary volumes in a synchronous replication relationship' [patent_app_type] => utility [patent_app_number] => 13/792794 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792794 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/792794
Protection of former primary volumes in a synchronous replication relationship Mar 10, 2013 Issued
Array ( [id] => 10131055 [patent_doc_number] => 09164890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Storage device capable of increasing its life cycle and operating method thereof' [patent_app_type] => utility [patent_app_number] => 13/792696 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7025 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792696 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/792696
Storage device capable of increasing its life cycle and operating method thereof Mar 10, 2013 Issued
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