Search

Frank E. Werner

Examiner (ID: 9818)

Most Active Art Unit
3107
Art Unit(s)
3617, 3104, 3106, 3107, 3652, 2899
Total Applications
1492
Issued Applications
1247
Pending Applications
54
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20310827 [patent_doc_number] => 20250328456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => Window-Based Memory Dependency Predictor [patent_app_type] => utility [patent_app_number] => 19/067080 [patent_app_country] => US [patent_app_date] => 2025-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19067080 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/067080
Window-Based Memory Dependency Predictor Feb 27, 2025 Pending
Array ( [id] => 19864496 [patent_doc_number] => 20250103282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => NEURAL PROCESSING DEVICE AND METHOD FOR CONVERTING DATA THEREOF [patent_app_type] => utility [patent_app_number] => 18/977667 [patent_app_country] => US [patent_app_date] => 2024-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18977667 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/977667
NEURAL PROCESSING DEVICE AND METHOD FOR CONVERTING DATA THEREOF Dec 10, 2024 Pending
Array ( [id] => 20061478 [patent_doc_number] => 20250199700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => COMPUTER SYSTEM AND METHOD FOR PERFORMING A RANDOM ACCESS OF A BIT IN A MEMORY [patent_app_type] => utility [patent_app_number] => 18/977736 [patent_app_country] => US [patent_app_date] => 2024-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18977736 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/977736
COMPUTER SYSTEM AND METHOD FOR PERFORMING A RANDOM ACCESS OF A BIT IN A MEMORY Dec 10, 2024 Pending
Array ( [id] => 19849006 [patent_doc_number] => 20250094357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => Cache Control to Preserve Register Data [patent_app_type] => utility [patent_app_number] => 18/962158 [patent_app_country] => US [patent_app_date] => 2024-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18962158 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/962158
Cache Control to Preserve Register Data Nov 26, 2024 Pending
Array ( [id] => 19802646 [patent_doc_number] => 20250068571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => OPERATING METHOD OF AN ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/940938 [patent_app_country] => US [patent_app_date] => 2024-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18940938 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/940938
OPERATING METHOD OF AN ELECTRONIC DEVICE Nov 7, 2024 Pending
Array ( [id] => 19787198 [patent_doc_number] => 20250060877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => METADATA REGISTERS FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/939310 [patent_app_country] => US [patent_app_date] => 2024-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18939310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/939310
METADATA REGISTERS FOR A MEMORY DEVICE Nov 5, 2024 Pending
Array ( [id] => 20461049 [patent_doc_number] => 20260010477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => SYSTEMS AND METHODS FOR PORT BASED ROUTING FOR SCALABLE MEMORY [patent_app_type] => utility [patent_app_number] => 18/927442 [patent_app_country] => US [patent_app_date] => 2024-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18927442 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/927442
SYSTEMS AND METHODS FOR PORT BASED ROUTING FOR SCALABLE MEMORY Oct 24, 2024 Pending
Array ( [id] => 20454793 [patent_doc_number] => 12517847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => System and method of handling modification tracking data in timestep shared memory multi-processors (TSMP) [patent_app_type] => utility [patent_app_number] => 18/905885 [patent_app_country] => US [patent_app_date] => 2024-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1273 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18905885 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/905885
System and method of handling modification tracking data in timestep shared memory multi-processors (TSMP) Oct 2, 2024 Issued
Array ( [id] => 19660431 [patent_doc_number] => 20240427496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => METHOD OF IMPROVING PROGRAMMING OPERATIONS IN 3D NAND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/824573 [patent_app_country] => US [patent_app_date] => 2024-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18824573 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/824573
METHOD OF IMPROVING PROGRAMMING OPERATIONS IN 3D NAND SYSTEMS Sep 3, 2024 Pending
Array ( [id] => 19864691 [patent_doc_number] => 20250103477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => Memory Controller Reservation of Resources for Cache Hit [patent_app_type] => utility [patent_app_number] => 18/819877 [patent_app_country] => US [patent_app_date] => 2024-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18819877 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/819877
Memory Controller Reservation of Resources for Cache Hit Aug 28, 2024 Pending
Array ( [id] => 19848998 [patent_doc_number] => 20250094349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/818781 [patent_app_country] => US [patent_app_date] => 2024-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 370 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18818781 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/818781
Processor Aug 28, 2024 Issued
Array ( [id] => 19617268 [patent_doc_number] => 20240402948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => STORAGE POLICY CHANGE USAGE ESTIMATION [patent_app_type] => utility [patent_app_number] => 18/802833 [patent_app_country] => US [patent_app_date] => 2024-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18802833 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/802833
STORAGE POLICY CHANGE USAGE ESTIMATION Aug 12, 2024 Pending
Array ( [id] => 20052126 [patent_doc_number] => 20250190348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => PROCESSOR AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/797046 [patent_app_country] => US [patent_app_date] => 2024-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18797046 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/797046
PROCESSOR AND ELECTRONIC DEVICE INCLUDING THE SAME Aug 6, 2024 Pending
Array ( [id] => 19711093 [patent_doc_number] => 20250021235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => HIGH-THROUGHPUT LOW-LATENCY HYBRID MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 18/794280 [patent_app_country] => US [patent_app_date] => 2024-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18794280 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/794280
High-throughput low-latency hybrid memory module Aug 4, 2024 Issued
Array ( [id] => 20331575 [patent_doc_number] => 12461852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Raid region alignment for FDP compliant SSD [patent_app_type] => utility [patent_app_number] => 18/775184 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18775184 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/775184
Raid region alignment for FDP compliant SSD Jul 16, 2024 Issued
Array ( [id] => 19481816 [patent_doc_number] => 20240329858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SYSTEM AND METHOD OF PERFORMING A READ OPERATION [patent_app_type] => utility [patent_app_number] => 18/739841 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739841 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739841
System and method of performing a read operation Jun 10, 2024 Issued
Array ( [id] => 19603321 [patent_doc_number] => 20240394201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => CABLE BANDWIDTH EXTENDER [patent_app_type] => utility [patent_app_number] => 18/671871 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671871 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671871
CABLE BANDWIDTH EXTENDER May 21, 2024 Pending
Array ( [id] => 20234409 [patent_doc_number] => 20250291728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => ADDRESS TRANSLATION SERVICES TO ENABLE MEMORY COHERENCE [patent_app_type] => utility [patent_app_number] => 18/665382 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665382 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/665382
ADDRESS TRANSLATION SERVICES TO ENABLE MEMORY COHERENCE May 14, 2024 Pending
Array ( [id] => 20265722 [patent_doc_number] => 12436713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Memory system using host memory buffer and operation method thereof [patent_app_type] => utility [patent_app_number] => 18/662090 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662090 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662090
Memory system using host memory buffer and operation method thereof May 12, 2024 Issued
Array ( [id] => 19362709 [patent_doc_number] => 20240264743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => ADDRESS TRANSLATION METADATA COMPRESSION IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/636783 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636783 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636783
Address translation metadata compression in memory devices Apr 15, 2024 Issued
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