Search

Frank E. Werner

Examiner (ID: 9818)

Most Active Art Unit
3107
Art Unit(s)
3617, 3104, 3106, 3107, 3652, 2899
Total Applications
1492
Issued Applications
1247
Pending Applications
54
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19347164 [patent_doc_number] => 20240256127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => HOST RATE ADJUSTMENT USING FREE SPACE VALUES [patent_app_type] => utility [patent_app_number] => 18/629743 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629743 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/629743
Host rate adjustment using free space values Apr 7, 2024 Issued
Array ( [id] => 19334426 [patent_doc_number] => 20240248856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => MEMORY ADDRESS COMPRESSION WITHIN AN EXECUTION TRACE [patent_app_type] => utility [patent_app_number] => 18/625675 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625675 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625675
Memory address compression within an execution trace Apr 2, 2024 Issued
Array ( [id] => 20281906 [patent_doc_number] => 20250307148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => SCOPE TREE CONSISTENCY PROTOCOL FOR CACHE COHERENCE [patent_app_type] => utility [patent_app_number] => 18/625084 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625084 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625084
SCOPE TREE CONSISTENCY PROTOCOL FOR CACHE COHERENCE Apr 1, 2024 Pending
Array ( [id] => 20281907 [patent_doc_number] => 20250307149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => SCOPE TREE CONSISTENCY PROTOCOL FOR CACHE COHERENCE [patent_app_type] => utility [patent_app_number] => 18/625106 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625106
SCOPE TREE CONSISTENCY PROTOCOL FOR CACHE COHERENCE Apr 1, 2024 Pending
Array ( [id] => 20281903 [patent_doc_number] => 20250307145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => Storing Indications of Cleared Cache Lines [patent_app_type] => utility [patent_app_number] => 18/618575 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618575 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618575
Storing indications of cleared cache lines Mar 26, 2024 Issued
Array ( [id] => 19617525 [patent_doc_number] => 20240403205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => NEAR-MEMORY PROTOCOL ANALYZER [patent_app_type] => utility [patent_app_number] => 18/615046 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615046 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615046
NEAR-MEMORY PROTOCOL ANALYZER Mar 24, 2024 Pending
Array ( [id] => 19925017 [patent_doc_number] => 12299299 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-13 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 18/601776 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601776
Memory system Mar 10, 2024 Issued
Array ( [id] => 19251145 [patent_doc_number] => 20240202135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/593823 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593823 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/593823
Memory system and method for controlling nonvolatile memory Feb 29, 2024 Issued
Array ( [id] => 19391511 [patent_doc_number] => 20240281381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => DATA STORAGE APPARATUS AND DATA PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 18/592356 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14016 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18592356 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/592356
DATA STORAGE APPARATUS AND DATA PROCESSING METHOD Feb 28, 2024 Pending
Array ( [id] => 19250917 [patent_doc_number] => 20240201907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => DATA PROCESSING METHOD, DATA PROCESSING APPARATUS, AND RELATED DEVICE [patent_app_type] => utility [patent_app_number] => 18/589722 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589722 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/589722
Data processing method, data processing apparatus, and related device Feb 27, 2024 Issued
Array ( [id] => 19771880 [patent_doc_number] => 20250053306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => METHOD, ELECTRONIC DEVICE, AND PROGRAM PRODUCT FOR DISK MAPPING [patent_app_type] => utility [patent_app_number] => 18/586999 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18586999 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/586999
Method, electronic device, and program product for disk mapping Feb 25, 2024 Issued
Array ( [id] => 19383154 [patent_doc_number] => 20240273024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => Scalable Cache Coherency Protocol [patent_app_type] => utility [patent_app_number] => 18/582333 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582333 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/582333
Scalable cache coherency protocol Feb 19, 2024 Issued
Array ( [id] => 19235891 [patent_doc_number] => 20240193086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => ON-DEMAND SCANNING FOR CHANGES IN CLOUD OBJECT STORAGE SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/582527 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582527 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/582527
On-demand scanning for changes in cloud object storage systems Feb 19, 2024 Issued
Array ( [id] => 19219742 [patent_doc_number] => 20240184446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS [patent_app_type] => utility [patent_app_number] => 18/441279 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441279 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441279
Multi-processor bridge with cache allocate awareness Feb 13, 2024 Issued
Array ( [id] => 19434462 [patent_doc_number] => 20240302960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => DISTRIBUTED ARCHITECTURE FOR INFORMATION MANAGEMENT SERVICES IN CLOUD ENVIRONMENTS [patent_app_type] => utility [patent_app_number] => 18/431590 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431590 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/431590
DISTRIBUTED ARCHITECTURE FOR INFORMATION MANAGEMENT SERVICES IN CLOUD ENVIRONMENTS Feb 1, 2024 Pending
Array ( [id] => 19320284 [patent_doc_number] => 20240241828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => DEVICE AND METHOD WITH CACHE COHERENCY MAINTENANCE FOR PIM OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/415083 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415083 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415083
DEVICE AND METHOD WITH CACHE COHERENCY MAINTENANCE FOR PIM OPERATIONS Jan 16, 2024 Pending
Array ( [id] => 20101943 [patent_doc_number] => 20250231879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => USING DIRECTORY DELEGATION FOR CLIENT SIDE CACHE OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/411266 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411266 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411266
USING DIRECTORY DELEGATION FOR CLIENT SIDE CACHE OPERATIONS Jan 11, 2024 Issued
Array ( [id] => 19971177 [patent_doc_number] => 12339788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Block or page lock features in serial interface memory [patent_app_type] => utility [patent_app_number] => 18/406423 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406423 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406423
Block or page lock features in serial interface memory Jan 7, 2024 Issued
Array ( [id] => 19283676 [patent_doc_number] => 20240220152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => METHOD AND DEVICE FOR READING CONFIGURATION DATA OF AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/393878 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18393878 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/393878
METHOD AND DEVICE FOR READING CONFIGURATION DATA OF AN INTEGRATED CIRCUIT Dec 21, 2023 Pending
Array ( [id] => 20388204 [patent_doc_number] => 12487930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Dynamic accounting of cache for GPU scratch memory usage [patent_app_type] => utility [patent_app_number] => 18/537716 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537716 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/537716
Dynamic accounting of cache for GPU scratch memory usage Dec 11, 2023 Issued
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