Search

Frank G. Font

Examiner (ID: 19387, Phone: (571)272-2415 , Office: P/2872 )

Most Active Art Unit
2501
Art Unit(s)
2501, 2606, 2899, 2872, 2504, 2877, 2883, 2505
Total Applications
2010
Issued Applications
1842
Pending Applications
7
Abandoned Applications
164

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4346333 [patent_doc_number] => 06330641 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Method and apparatus for controlling magnetic disk device' [patent_app_type] => 1 [patent_app_number] => 9/314134 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4222 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330641.pdf [firstpage_image] =>[orig_patent_app_number] => 314134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314134
Method and apparatus for controlling magnetic disk device May 18, 1999 Issued
Array ( [id] => 4422461 [patent_doc_number] => 06173367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method and apparatus for accessing graphics cache memory' [patent_app_type] => 1 [patent_app_number] => 9/314210 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6774 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173367.pdf [firstpage_image] =>[orig_patent_app_number] => 314210 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314210
Method and apparatus for accessing graphics cache memory May 18, 1999 Issued
Array ( [id] => 4424570 [patent_doc_number] => 06266754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Secure computing device including operating system stored in non-relocatable page of memory' [patent_app_type] => 1 [patent_app_number] => 9/314397 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7952 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266754.pdf [firstpage_image] =>[orig_patent_app_number] => 314397 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314397
Secure computing device including operating system stored in non-relocatable page of memory May 18, 1999 Issued
Array ( [id] => 4349723 [patent_doc_number] => 06321309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Memory arbitration scheme with circular sequence register' [patent_app_type] => 1 [patent_app_number] => 9/314655 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1733 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321309.pdf [firstpage_image] =>[orig_patent_app_number] => 314655 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314655
Memory arbitration scheme with circular sequence register May 18, 1999 Issued
Array ( [id] => 1365219 [patent_doc_number] => 06581135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-17 [patent_title] => 'Information storage system for redistributing information to information storage devices when a structure of the information storage devices is changed' [patent_app_type] => B2 [patent_app_number] => 09/314384 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 50 [patent_no_of_words] => 16189 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581135.pdf [firstpage_image] =>[orig_patent_app_number] => 09314384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314384
Information storage system for redistributing information to information storage devices when a structure of the information storage devices is changed May 18, 1999 Issued
Array ( [id] => 1466244 [patent_doc_number] => 06393536 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Load/store unit employing last-in-buffer indication for rapid load-hit-store' [patent_app_type] => B1 [patent_app_number] => 09/314180 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 21167 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393536.pdf [firstpage_image] =>[orig_patent_app_number] => 09314180 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314180
Load/store unit employing last-in-buffer indication for rapid load-hit-store May 17, 1999 Issued
Array ( [id] => 4333210 [patent_doc_number] => 06317813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Method for arbitrating multiple memory access requests in a unified memory architecture via a non unified memory controller' [patent_app_type] => 1 [patent_app_number] => 9/314245 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5575 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317813.pdf [firstpage_image] =>[orig_patent_app_number] => 314245 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314245
Method for arbitrating multiple memory access requests in a unified memory architecture via a non unified memory controller May 17, 1999 Issued
Array ( [id] => 1524882 [patent_doc_number] => 06415360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Minimizing self-modifying code checks for uncacheable memory types' [patent_app_type] => B1 [patent_app_number] => 09/314066 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 28058 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415360.pdf [firstpage_image] =>[orig_patent_app_number] => 09314066 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314066
Minimizing self-modifying code checks for uncacheable memory types May 17, 1999 Issued
Array ( [id] => 1466195 [patent_doc_number] => 06393525 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Least recently used replacement method with protection' [patent_app_type] => B1 [patent_app_number] => 09/314233 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5744 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393525.pdf [firstpage_image] =>[orig_patent_app_number] => 09314233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314233
Least recently used replacement method with protection May 17, 1999 Issued
Array ( [id] => 1406498 [patent_doc_number] => 06560669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Double data rate synchronous memory with block-write' [patent_app_type] => B1 [patent_app_number] => 09/314056 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 5959 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560669.pdf [firstpage_image] =>[orig_patent_app_number] => 09314056 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314056
Double data rate synchronous memory with block-write May 17, 1999 Issued
Array ( [id] => 1210377 [patent_doc_number] => 06718445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'System and method for performing dynamic buffer management in an HFS (hierarchical file system DF/SMS)' [patent_app_type] => B1 [patent_app_number] => 09/280796 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4557 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718445.pdf [firstpage_image] =>[orig_patent_app_number] => 09280796 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280796
System and method for performing dynamic buffer management in an HFS (hierarchical file system DF/SMS) Mar 25, 1999 Issued
Array ( [id] => 1552695 [patent_doc_number] => 06446141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Storage server system including ranking of data source' [patent_app_type] => B1 [patent_app_number] => 09/276428 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 12214 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446141.pdf [firstpage_image] =>[orig_patent_app_number] => 09276428 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/276428
Storage server system including ranking of data source Mar 24, 1999 Issued
Array ( [id] => 1557521 [patent_doc_number] => 06401171 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method and device for storing an IP header in a cache memory of a network node' [patent_app_type] => B1 [patent_app_number] => 09/261604 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2534 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401171.pdf [firstpage_image] =>[orig_patent_app_number] => 09261604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/261604
Method and device for storing an IP header in a cache memory of a network node Feb 25, 1999 Issued
Array ( [id] => 1553771 [patent_doc_number] => 06347359 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Method for reconfiguration of RAID data storage systems' [patent_app_type] => B1 [patent_app_number] => 09/253106 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4904 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347359.pdf [firstpage_image] =>[orig_patent_app_number] => 09253106 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/253106
Method for reconfiguration of RAID data storage systems Feb 18, 1999 Issued
Array ( [id] => 4350730 [patent_doc_number] => 06334168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Method and system for updating data in a data storage system' [patent_app_type] => 1 [patent_app_number] => 9/253413 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5039 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/334/06334168.pdf [firstpage_image] =>[orig_patent_app_number] => 253413 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/253413
Method and system for updating data in a data storage system Feb 18, 1999 Issued
Array ( [id] => 7638625 [patent_doc_number] => 06397296 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Two-level instruction cache for embedded processors' [patent_app_type] => B1 [patent_app_number] => 09/252838 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6622 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397296.pdf [firstpage_image] =>[orig_patent_app_number] => 09252838 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252838
Two-level instruction cache for embedded processors Feb 18, 1999 Issued
Array ( [id] => 1526483 [patent_doc_number] => 06353879 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Memory address translation in a data processing system' [patent_app_type] => B1 [patent_app_number] => 09/252927 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3083 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353879.pdf [firstpage_image] =>[orig_patent_app_number] => 09252927 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252927
Memory address translation in a data processing system Feb 18, 1999 Issued
Array ( [id] => 1484884 [patent_doc_number] => 06453366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method and apparatus for direct memory access (DMA) with dataflow blocking for users' [patent_app_type] => B1 [patent_app_number] => 09/251043 [patent_app_country] => US [patent_app_date] => 1999-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1905 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453366.pdf [firstpage_image] =>[orig_patent_app_number] => 09251043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251043
Method and apparatus for direct memory access (DMA) with dataflow blocking for users Feb 17, 1999 Issued
Array ( [id] => 4350815 [patent_doc_number] => 06334174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Dynamically-tunable memory controller' [patent_app_type] => 1 [patent_app_number] => 9/247501 [patent_app_country] => US [patent_app_date] => 1999-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 14653 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/334/06334174.pdf [firstpage_image] =>[orig_patent_app_number] => 247501 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/247501
Dynamically-tunable memory controller Feb 9, 1999 Issued
Array ( [id] => 1540543 [patent_doc_number] => 06490652 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Method and apparatus for decoupled retrieval of cache miss data' [patent_app_type] => B1 [patent_app_number] => 09/244692 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 14942 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490652.pdf [firstpage_image] =>[orig_patent_app_number] => 09244692 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244692
Method and apparatus for decoupled retrieval of cache miss data Feb 2, 1999 Issued
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