Search

Frank J. Asta

Examiner (ID: 7986)

Most Active Art Unit
2312
Art Unit(s)
2752, 2318, 2312, 2756
Total Applications
250
Issued Applications
208
Pending Applications
4
Abandoned Applications
38

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3460356 [patent_doc_number] => 05386539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'IC memory card comprising an EEPROM with data and address buffering for controlling the writing/reading of data to EEPROM' [patent_app_type] => 1 [patent_app_number] => 7/751982 [patent_app_country] => US [patent_app_date] => 1991-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2895 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386539.pdf [firstpage_image] =>[orig_patent_app_number] => 751982 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/751982
IC memory card comprising an EEPROM with data and address buffering for controlling the writing/reading of data to EEPROM Aug 28, 1991 Issued
07/751590 CACHE CONTROLLER Aug 21, 1991 Abandoned
07/744587 IMAGING AND GRAPHICS PROCESSING SYSTEM Aug 12, 1991 Abandoned
07/739370 TECHNIQUE TO SUPPORT PROGRESSIVELY PROGRAMMABLE NONVOLATILE MEMORY Aug 1, 1991 Abandoned
Array ( [id] => 3004180 [patent_doc_number] => 05347640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'Circuit for generating addresses for buffering and reading the data from a CD-ROM and method therefor' [patent_app_type] => 1 [patent_app_number] => 7/732144 [patent_app_country] => US [patent_app_date] => 1991-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 3370 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/347/05347640.pdf [firstpage_image] =>[orig_patent_app_number] => 732144 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/732144
Circuit for generating addresses for buffering and reading the data from a CD-ROM and method therefor Jul 17, 1991 Issued
Array ( [id] => 3079432 [patent_doc_number] => 05353423 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-04 [patent_title] => 'Memory controller for use with write-back cache system and multiple bus masters coupled to multiple buses' [patent_app_type] => 1 [patent_app_number] => 7/719030 [patent_app_country] => US [patent_app_date] => 1991-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 31 [patent_no_of_words] => 15791 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/353/05353423.pdf [firstpage_image] =>[orig_patent_app_number] => 719030 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/719030
Memory controller for use with write-back cache system and multiple bus masters coupled to multiple buses Jun 20, 1991 Issued
Array ( [id] => 3053325 [patent_doc_number] => 05377342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Method of controlling a duplex data storage system and data processing system using the same' [patent_app_type] => 1 [patent_app_number] => 7/715580 [patent_app_country] => US [patent_app_date] => 1991-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 7226 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/377/05377342.pdf [firstpage_image] =>[orig_patent_app_number] => 715580 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/715580
Method of controlling a duplex data storage system and data processing system using the same Jun 13, 1991 Issued
Array ( [id] => 3021189 [patent_doc_number] => 05355465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'Data storing device having a plurality of registers allotted for one address' [patent_app_type] => 1 [patent_app_number] => 7/712440 [patent_app_country] => US [patent_app_date] => 1991-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2289 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/355/05355465.pdf [firstpage_image] =>[orig_patent_app_number] => 712440 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/712440
Data storing device having a plurality of registers allotted for one address Jun 10, 1991 Issued
Array ( [id] => 3033515 [patent_doc_number] => 05289477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-22 [patent_title] => 'Personal computer wherein ECC and partly error checking can be selectively chosen for memory elements installed in the system, memory elements enabling selective choice of error checking, and method' [patent_app_type] => 1 [patent_app_number] => 7/711480 [patent_app_country] => US [patent_app_date] => 1991-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5197 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/289/05289477.pdf [firstpage_image] =>[orig_patent_app_number] => 711480 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/711480
Personal computer wherein ECC and partly error checking can be selectively chosen for memory elements installed in the system, memory elements enabling selective choice of error checking, and method Jun 5, 1991 Issued
Array ( [id] => 3049927 [patent_doc_number] => 05301295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Data processor apparatus and method with selective caching of instructions' [patent_app_type] => 1 [patent_app_number] => 7/704290 [patent_app_country] => US [patent_app_date] => 1991-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3763 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/301/05301295.pdf [firstpage_image] =>[orig_patent_app_number] => 704290 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/704290
Data processor apparatus and method with selective caching of instructions May 21, 1991 Issued
07/691622 PARTITIONING OF VIRTUAL ADDRSSING MEMORY Apr 24, 1991 Abandoned
Array ( [id] => 3110582 [patent_doc_number] => 05293607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-08 [patent_title] => 'Flexible N-way memory interleaving' [patent_app_type] => 1 [patent_app_number] => 7/679868 [patent_app_country] => US [patent_app_date] => 1991-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4126 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/293/05293607.pdf [firstpage_image] =>[orig_patent_app_number] => 679868 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/679868
Flexible N-way memory interleaving Apr 2, 1991 Issued
07/672667 MEMORY SELECTION CIRCUIT Mar 20, 1991 Abandoned
07/670697 A CACHE MEMORY SYSTEM THAT ACCESSES MAIN MEMORY WITHOUT WAIT STATES DURING CACHE MISSES, USING A STATE MACHINE AND ADDRESS LATCH IN THE MEMORY CONTROLLER Mar 17, 1991 Abandoned
Array ( [id] => 2948272 [patent_doc_number] => 05247645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'Dynamic memory mapper which supports interleaving across 2.sup.N +1, 2.sup. N .sup.N -1 number of banks for reducing contention during nonunit stride accesses' [patent_app_type] => 1 [patent_app_number] => 7/668007 [patent_app_country] => US [patent_app_date] => 1991-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5593 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/247/05247645.pdf [firstpage_image] =>[orig_patent_app_number] => 668007 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/668007
Dynamic memory mapper which supports interleaving across 2.sup.N +1, 2.sup. N .sup.N -1 number of banks for reducing contention during nonunit stride accesses Mar 11, 1991 Issued
Array ( [id] => 3626392 [patent_doc_number] => 05535366 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Method of and circuit arrangement for freeing communications resources, particularly for use by a switching element' [patent_app_type] => 1 [patent_app_number] => 7/665788 [patent_app_country] => US [patent_app_date] => 1991-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 4482 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535366.pdf [firstpage_image] =>[orig_patent_app_number] => 665788 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/665788
Method of and circuit arrangement for freeing communications resources, particularly for use by a switching element Mar 5, 1991 Issued
07/643961 SYSTEM FOR CONTROLLING AN INTERNALLY-INSTALLED CACHE MEMORY Jan 21, 1991 Abandoned
Array ( [id] => 2924877 [patent_doc_number] => 05228136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'Method and apparatus to maintain cache coherency in a multiprocessor system with each processor\'s private cache updating or invalidating its contents based upon set activity' [patent_app_type] => 1 [patent_app_number] => 7/639440 [patent_app_country] => US [patent_app_date] => 1991-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4984 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/228/05228136.pdf [firstpage_image] =>[orig_patent_app_number] => 639440 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/639440
Method and apparatus to maintain cache coherency in a multiprocessor system with each processor's private cache updating or invalidating its contents based upon set activity Jan 9, 1991 Issued
Array ( [id] => 2988588 [patent_doc_number] => 05226139 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Semiconductor memory device with a built-in cache memory and operating method thereof' [patent_app_type] => 1 [patent_app_number] => 7/637872 [patent_app_country] => US [patent_app_date] => 1991-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 7926 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226139.pdf [firstpage_image] =>[orig_patent_app_number] => 637872 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/637872
Semiconductor memory device with a built-in cache memory and operating method thereof Jan 7, 1991 Issued
Array ( [id] => 2908215 [patent_doc_number] => 05241664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-31 [patent_title] => 'Multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 7/637902 [patent_app_country] => US [patent_app_date] => 1991-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5727 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/241/05241664.pdf [firstpage_image] =>[orig_patent_app_number] => 637902 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/637902
Multiprocessor system Jan 6, 1991 Issued
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