Search

Frank J. Asta

Examiner (ID: 7986)

Most Active Art Unit
2312
Art Unit(s)
2752, 2318, 2312, 2756
Total Applications
250
Issued Applications
208
Pending Applications
4
Abandoned Applications
38

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3062827 [patent_doc_number] => 05283880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-01 [patent_title] => 'Method of fast buffer copying by utilizing a cache memory to accept a page of source buffer contents and then supplying these contents to a target buffer without causing unnecessary wait states' [patent_app_type] => 1 [patent_app_number] => 7/636732 [patent_app_country] => US [patent_app_date] => 1991-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7953 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/283/05283880.pdf [firstpage_image] =>[orig_patent_app_number] => 636732 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/636732
Method of fast buffer copying by utilizing a cache memory to accept a page of source buffer contents and then supplying these contents to a target buffer without causing unnecessary wait states Jan 1, 1991 Issued
Array ( [id] => 2977130 [patent_doc_number] => 05265226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-23 [patent_title] => 'Memory access methods and apparatus' [patent_app_type] => 1 [patent_app_number] => 7/633350 [patent_app_country] => US [patent_app_date] => 1990-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8127 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/265/05265226.pdf [firstpage_image] =>[orig_patent_app_number] => 633350 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/633350
Memory access methods and apparatus Dec 26, 1990 Issued
Array ( [id] => 2915674 [patent_doc_number] => 05249283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'Cache coherency method and apparatus for a multiple path interconnection network' [patent_app_type] => 1 [patent_app_number] => 7/633732 [patent_app_country] => US [patent_app_date] => 1990-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3817 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/249/05249283.pdf [firstpage_image] =>[orig_patent_app_number] => 633732 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/633732
Cache coherency method and apparatus for a multiple path interconnection network Dec 23, 1990 Issued
07/630300 A MEMORY ACCESS SYSTEM AND METHOD FOR GRANTING OR PREVENTING ATOMIC OR NONATOMIC MEMORY ACCESS REQUESTS TO SHARED MEMORY REGIONS Dec 18, 1990 Abandoned
Array ( [id] => 3062810 [patent_doc_number] => 05283879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-01 [patent_title] => 'Protected method for fast writing of data for mass memory apparatus' [patent_app_type] => 1 [patent_app_number] => 7/631722 [patent_app_country] => US [patent_app_date] => 1990-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7350 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 436 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/283/05283879.pdf [firstpage_image] =>[orig_patent_app_number] => 631722 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/631722
Protected method for fast writing of data for mass memory apparatus Dec 18, 1990 Issued
Array ( [id] => 2988703 [patent_doc_number] => 05226145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Storage management system for memory card using memory allocation table' [patent_app_type] => 1 [patent_app_number] => 7/622033 [patent_app_country] => US [patent_app_date] => 1990-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 8701 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226145.pdf [firstpage_image] =>[orig_patent_app_number] => 622033 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/622033
Storage management system for memory card using memory allocation table Dec 3, 1990 Issued
Array ( [id] => 2882895 [patent_doc_number] => 05163143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-10 [patent_title] => 'Enhanced locked bus cycle control in a cache memory computer system' [patent_app_type] => 1 [patent_app_number] => 7/431742 [patent_app_country] => US [patent_app_date] => 1990-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4547 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/163/05163143.pdf [firstpage_image] =>[orig_patent_app_number] => 431742 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/431742
Enhanced locked bus cycle control in a cache memory computer system Nov 2, 1990 Issued
07/607657 DATA PROCESSING SYSTEM Oct 30, 1990 Abandoned
Array ( [id] => 2934330 [patent_doc_number] => 05235694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-10 [patent_title] => 'Multi I/O device system using temporary store of RAM data when associated communicating I/O devices are operating at various clocking phases' [patent_app_type] => 1 [patent_app_number] => 7/605356 [patent_app_country] => US [patent_app_date] => 1990-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3033 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/235/05235694.pdf [firstpage_image] =>[orig_patent_app_number] => 605356 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/605356
Multi I/O device system using temporary store of RAM data when associated communicating I/O devices are operating at various clocking phases Oct 29, 1990 Issued
Array ( [id] => 2930066 [patent_doc_number] => 05193170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'Methods and apparatus for maintaining cache integrity whenever a CPU write to ROM operation is performed with ROM mapped to RAM' [patent_app_type] => 1 [patent_app_number] => 7/604837 [patent_app_country] => US [patent_app_date] => 1990-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5586 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/193/05193170.pdf [firstpage_image] =>[orig_patent_app_number] => 604837 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/604837
Methods and apparatus for maintaining cache integrity whenever a CPU write to ROM operation is performed with ROM mapped to RAM Oct 25, 1990 Issued
Array ( [id] => 2989857 [patent_doc_number] => 05257361 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-26 [patent_title] => 'Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation' [patent_app_type] => 1 [patent_app_number] => 7/603620 [patent_app_country] => US [patent_app_date] => 1990-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 8571 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/257/05257361.pdf [firstpage_image] =>[orig_patent_app_number] => 603620 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/603620
Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation Oct 25, 1990 Issued
Array ( [id] => 2905154 [patent_doc_number] => 05210852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-11 [patent_title] => 'Memory control system for controlling a first and second processing means to individually access a plurality of memory blocks' [patent_app_type] => 1 [patent_app_number] => 7/602097 [patent_app_country] => US [patent_app_date] => 1990-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4001 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/210/05210852.pdf [firstpage_image] =>[orig_patent_app_number] => 602097 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/602097
Memory control system for controlling a first and second processing means to individually access a plurality of memory blocks Oct 22, 1990 Issued
Array ( [id] => 2929914 [patent_doc_number] => 05193164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'Data deskewing apparatus utilizing bank switched random access memories' [patent_app_type] => 1 [patent_app_number] => 7/601548 [patent_app_country] => US [patent_app_date] => 1990-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4680 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/193/05193164.pdf [firstpage_image] =>[orig_patent_app_number] => 601548 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/601548
Data deskewing apparatus utilizing bank switched random access memories Oct 21, 1990 Issued
Array ( [id] => 3024115 [patent_doc_number] => 05333294 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'Configurable data width direct memory access device with a read address counter and a write address counter which increments the addresses based on the desired data transfer width' [patent_app_type] => 1 [patent_app_number] => 7/594601 [patent_app_country] => US [patent_app_date] => 1990-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5336 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/333/05333294.pdf [firstpage_image] =>[orig_patent_app_number] => 594601 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/594601
Configurable data width direct memory access device with a read address counter and a write address counter which increments the addresses based on the desired data transfer width Oct 8, 1990 Issued
07/592098 A DMA CONTROLLER USING A PROGRAMMABLE TIMER, A TRANSFER COUNTER AND AN OF LOGIC GATE TO CONTROL DATA TRANSFER INTERRUPTS Oct 2, 1990 Abandoned
Array ( [id] => 2929895 [patent_doc_number] => 05193163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'Two-level protocol for multi-component bus ownership, and implementation in a multi-processor cache write back protocol' [patent_app_type] => 1 [patent_app_number] => 7/591197 [patent_app_country] => US [patent_app_date] => 1990-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4709 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/193/05193163.pdf [firstpage_image] =>[orig_patent_app_number] => 591197 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/591197
Two-level protocol for multi-component bus ownership, and implementation in a multi-processor cache write back protocol Sep 30, 1990 Issued
Array ( [id] => 2924823 [patent_doc_number] => 05228133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'Method to perform text search in application programs in computer by selecting a character and scanning the text string to/from the selected character offset position' [patent_app_type] => 1 [patent_app_number] => 7/591068 [patent_app_country] => US [patent_app_date] => 1990-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5098 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/228/05228133.pdf [firstpage_image] =>[orig_patent_app_number] => 591068 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/591068
Method to perform text search in application programs in computer by selecting a character and scanning the text string to/from the selected character offset position Sep 30, 1990 Issued
Array ( [id] => 2988494 [patent_doc_number] => 05226134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Data processing system including a memory controller for direct or interleave memory accessing' [patent_app_type] => 1 [patent_app_number] => 7/591306 [patent_app_country] => US [patent_app_date] => 1990-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2072 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 580 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226134.pdf [firstpage_image] =>[orig_patent_app_number] => 591306 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/591306
Data processing system including a memory controller for direct or interleave memory accessing Sep 30, 1990 Issued
07/591198 METHOD AND APPARATUS FOR CONTROLLING A PROCESSOR BUS USED BY MULTIPLE PROCESSOR COMPONENTS DURING WRITEBACK CACHE TRANSACTIONS Sep 30, 1990 Abandoned
Array ( [id] => 3539635 [patent_doc_number] => 05528768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-18 [patent_title] => 'Multiprocessor communication system having a paritioned main memory where individual processors write to exclusive portions of the main memory and read from the entire main memory' [patent_app_type] => 1 [patent_app_number] => 7/590357 [patent_app_country] => US [patent_app_date] => 1990-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2524 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/528/05528768.pdf [firstpage_image] =>[orig_patent_app_number] => 590357 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/590357
Multiprocessor communication system having a paritioned main memory where individual processors write to exclusive portions of the main memory and read from the entire main memory Sep 27, 1990 Issued
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