Search

Frank J. Asta

Examiner (ID: 13044)

Most Active Art Unit
2312
Art Unit(s)
2318, 2752, 2756, 2312
Total Applications
250
Issued Applications
208
Pending Applications
4
Abandoned Applications
38

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3539635 [patent_doc_number] => 05528768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-18 [patent_title] => 'Multiprocessor communication system having a paritioned main memory where individual processors write to exclusive portions of the main memory and read from the entire main memory' [patent_app_type] => 1 [patent_app_number] => 7/590357 [patent_app_country] => US [patent_app_date] => 1990-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2524 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/528/05528768.pdf [firstpage_image] =>[orig_patent_app_number] => 590357 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/590357
Multiprocessor communication system having a paritioned main memory where individual processors write to exclusive portions of the main memory and read from the entire main memory Sep 27, 1990 Issued
Array ( [id] => 2897053 [patent_doc_number] => 05269011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-07 [patent_title] => 'Dynamically reconfigurable data storage system with storage system controllers selectively operable as channel adapters on storage device adapters' [patent_app_type] => 1 [patent_app_number] => 7/587247 [patent_app_country] => US [patent_app_date] => 1990-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/269/05269011.pdf [firstpage_image] =>[orig_patent_app_number] => 587247 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/587247
Dynamically reconfigurable data storage system with storage system controllers selectively operable as channel adapters on storage device adapters Sep 23, 1990 Issued
Array ( [id] => 2958701 [patent_doc_number] => 05255382 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-19 [patent_title] => 'Program memory expander for 8051-based microcontrolled system' [patent_app_type] => 1 [patent_app_number] => 7/587244 [patent_app_country] => US [patent_app_date] => 1990-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 9824 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/255/05255382.pdf [firstpage_image] =>[orig_patent_app_number] => 587244 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/587244
Program memory expander for 8051-based microcontrolled system Sep 23, 1990 Issued
07/584692 DATA PROCESSING DEVICE FOR MAINTAINING COHERENCY OF DATA STORED IN MAIN MEMORY, EXTERNAL CACHE MEMORY AND INTERNAL CACHE MEMORY Sep 18, 1990 Abandoned
07/580573 STABLE MEMORY CIRCUITS Sep 10, 1990 Abandoned
Array ( [id] => 2977208 [patent_doc_number] => 05265230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-23 [patent_title] => 'Method and apparatus for determining sector status in a data storage device by writing a status of read-only, writable, or obliterated in an error recovery area of each sector' [patent_app_type] => 1 [patent_app_number] => 7/574632 [patent_app_country] => US [patent_app_date] => 1990-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4416 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/265/05265230.pdf [firstpage_image] =>[orig_patent_app_number] => 574632 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/574632
Method and apparatus for determining sector status in a data storage device by writing a status of read-only, writable, or obliterated in an error recovery area of each sector Aug 28, 1990 Issued
Array ( [id] => 3016442 [patent_doc_number] => 05375213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-20 [patent_title] => 'Address translation device and method for managing address information using the device' [patent_app_type] => 1 [patent_app_number] => 7/574063 [patent_app_country] => US [patent_app_date] => 1990-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 8166 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/375/05375213.pdf [firstpage_image] =>[orig_patent_app_number] => 574063 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/574063
Address translation device and method for managing address information using the device Aug 28, 1990 Issued
07/553300 DATA PROCESSING DEVICE FOR PREVENTING INCONSISTENCY OF DATA STORED IN MAIN MEMORY AND CACHE MEMORY Jul 16, 1990 Abandoned
Array ( [id] => 2915612 [patent_doc_number] => 05249280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'Microcomputer having a memory bank switching apparatus for accessing a selected memory bank in an external memory' [patent_app_type] => 1 [patent_app_number] => 7/548695 [patent_app_country] => US [patent_app_date] => 1990-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4040 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/249/05249280.pdf [firstpage_image] =>[orig_patent_app_number] => 548695 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/548695
Microcomputer having a memory bank switching apparatus for accessing a selected memory bank in an external memory Jul 4, 1990 Issued
07/547995 CONVERSION OF INTERNAL PROCESSOR REGISTER COMMANDS TO I/O SPACE ADDRESSES Jun 28, 1990 Abandoned
Array ( [id] => 2980147 [patent_doc_number] => 05202973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus' [patent_app_type] => 1 [patent_app_number] => 7/546548 [patent_app_country] => US [patent_app_date] => 1990-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11331 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/202/05202973.pdf [firstpage_image] =>[orig_patent_app_number] => 546548 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/546548
Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus Jun 28, 1990 Issued
Array ( [id] => 2929967 [patent_doc_number] => 05193167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 7/547618 [patent_app_country] => US [patent_app_date] => 1990-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 13731 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/193/05193167.pdf [firstpage_image] =>[orig_patent_app_number] => 547618 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/547618
Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system Jun 28, 1990 Issued
07/547850 COMBINED QUEUE FOR INVALIDATES AND RETURN DATA IN MULTIPROCESSOR SYSTEM Jun 28, 1990 Abandoned
07/547699 PROCESSOR SYSTEM WITH WRITEBACK CACHE USING WRITEBACK AND NON WRITEBACK TRANSACTIONS STORED IN SEPARATE QUEUES Jun 28, 1990 Abandoned
Array ( [id] => 2849610 [patent_doc_number] => 05161220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-03 [patent_title] => 'Data write control circuit having word length conversion function' [patent_app_type] => 1 [patent_app_number] => 7/542599 [patent_app_country] => US [patent_app_date] => 1990-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7367 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 560 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/161/05161220.pdf [firstpage_image] =>[orig_patent_app_number] => 542599 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/542599
Data write control circuit having word length conversion function Jun 24, 1990 Issued
07/539026 LEAST RECENTLY USED REPLACEMENT APPARATUS FOR A SYSTEM WITH A SET ASSOCIATIVE CACHE Jun 14, 1990 Abandoned
07/537304 AN APPARATUS AND METHOD TO SET AND RESET A PIPLINE INSTRUCTION EXECUTION CONTROL UNIT FOR SEQUENTIAL EXECUTION OF AN INSTRUCTION INTERVAL Jun 12, 1990 Abandoned
Array ( [id] => 2934220 [patent_doc_number] => 05235688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-10 [patent_title] => 'Memory access control unit for allowing maximum throughput of an I/O processor and an I/O request buffer full state' [patent_app_type] => 1 [patent_app_number] => 7/532446 [patent_app_country] => US [patent_app_date] => 1990-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3998 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/235/05235688.pdf [firstpage_image] =>[orig_patent_app_number] => 532446 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/532446
Memory access control unit for allowing maximum throughput of an I/O processor and an I/O request buffer full state Jun 3, 1990 Issued
07/529866 SELECTIVELY LOCKING MEMORY LOCATIONS WITHIN A MICROPROCESSOR'S ON-CHIP CACHE May 28, 1990 Abandoned
Array ( [id] => 2913893 [patent_doc_number] => 05218687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-08 [patent_title] => 'Method and apparatus for fast memory access in a computer system' [patent_app_type] => 1 [patent_app_number] => 7/508931 [patent_app_country] => US [patent_app_date] => 1990-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7076 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/218/05218687.pdf [firstpage_image] =>[orig_patent_app_number] => 508931 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/508931
Method and apparatus for fast memory access in a computer system Apr 11, 1990 Issued
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