Search

Frank J. Asta

Examiner (ID: 7986)

Most Active Art Unit
2312
Art Unit(s)
2752, 2318, 2312, 2756
Total Applications
250
Issued Applications
208
Pending Applications
4
Abandoned Applications
38

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2988686 [patent_doc_number] => 05226144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Cache controller for maintaining cache coherency in a multiprocessor system including multiple data coherency procedures' [patent_app_type] => 1 [patent_app_number] => 7/463687 [patent_app_country] => US [patent_app_date] => 1990-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226144.pdf [firstpage_image] =>[orig_patent_app_number] => 463687 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/463687
Cache controller for maintaining cache coherency in a multiprocessor system including multiple data coherency procedures Jan 10, 1990 Issued
07/462546 COMPUTER SYSTEM WITH MEMORY EXPANSION FUNCTION AND EXPANSION MEMORY SETTING METHOD Jan 8, 1990 Abandoned
07/435320 PROGRAMMABLE CACHABLE MEMORY AREAS Nov 12, 1989 Abandoned
Array ( [id] => 2929876 [patent_doc_number] => 05193162 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'Cache memory with data compaction for use in the audit trail of a data processing system having record locking capabilities' [patent_app_type] => 1 [patent_app_number] => 7/432421 [patent_app_country] => US [patent_app_date] => 1989-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 7022 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 413 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/193/05193162.pdf [firstpage_image] =>[orig_patent_app_number] => 432421 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/432421
Cache memory with data compaction for use in the audit trail of a data processing system having record locking capabilities Nov 5, 1989 Issued
07/431670 A PAGE MODE MEMORY CONTRLLER FOR SYSTEM UTILIZING RAS SIGNALS, CAS SIGNALS, MINIMAL WAIT STATES AND MINIMAL MEMORY CYCLES IN ACCESS COMPLETION Nov 2, 1989 Abandoned
Array ( [id] => 2907792 [patent_doc_number] => 05241642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-31 [patent_title] => 'Image memory controller for controlling multiple memories and method of operation' [patent_app_type] => 1 [patent_app_number] => 7/414139 [patent_app_country] => US [patent_app_date] => 1989-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2998 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/241/05241642.pdf [firstpage_image] =>[orig_patent_app_number] => 414139 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/414139
Image memory controller for controlling multiple memories and method of operation Sep 27, 1989 Issued
Array ( [id] => 2988456 [patent_doc_number] => 05226132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Multiple virtual addressing using/comparing translation pairs of addresses comprising a space address and an origin address (STO) while using space registers as storage devices for a data processing system' [patent_app_type] => 1 [patent_app_number] => 7/413444 [patent_app_country] => US [patent_app_date] => 1989-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4743 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 379 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226132.pdf [firstpage_image] =>[orig_patent_app_number] => 413444 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/413444
Multiple virtual addressing using/comparing translation pairs of addresses comprising a space address and an origin address (STO) while using space registers as storage devices for a data processing system Sep 26, 1989 Issued
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