Search

Frank J. Asta

Examiner (ID: 14621)

Most Active Art Unit
2312
Art Unit(s)
2756, 2312, 2318, 2752
Total Applications
250
Issued Applications
208
Pending Applications
4
Abandoned Applications
38

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3596616 [patent_doc_number] => 05581785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Starting system of disk storage device and data reading/writing system of the same' [patent_app_type] => 1 [patent_app_number] => 8/278085 [patent_app_country] => US [patent_app_date] => 1994-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4545 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581785.pdf [firstpage_image] =>[orig_patent_app_number] => 278085 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/278085
Starting system of disk storage device and data reading/writing system of the same Jul 19, 1994 Issued
Array ( [id] => 3503294 [patent_doc_number] => 05561782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Pipelined cache system having low effective latency for nonsequential accesses' [patent_app_type] => 1 [patent_app_number] => 8/269650 [patent_app_country] => US [patent_app_date] => 1994-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4254 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561782.pdf [firstpage_image] =>[orig_patent_app_number] => 269650 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/269650
Pipelined cache system having low effective latency for nonsequential accesses Jun 29, 1994 Issued
Array ( [id] => 3595713 [patent_doc_number] => 05581728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Information storage system having advance reading function' [patent_app_type] => 1 [patent_app_number] => 8/262527 [patent_app_country] => US [patent_app_date] => 1994-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4996 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581728.pdf [firstpage_image] =>[orig_patent_app_number] => 262527 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/262527
Information storage system having advance reading function Jun 19, 1994 Issued
Array ( [id] => 3501517 [patent_doc_number] => 05471599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Partitioning of virtual addressing memory' [patent_app_type] => 1 [patent_app_number] => 8/228948 [patent_app_country] => US [patent_app_date] => 1994-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1680 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471599.pdf [firstpage_image] =>[orig_patent_app_number] => 228948 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/228948
Partitioning of virtual addressing memory Apr 17, 1994 Issued
Array ( [id] => 3437664 [patent_doc_number] => 05404466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Apparatus and method to set and reset a pipeline instruction execution control unit for sequential execution of an instruction interval' [patent_app_type] => 1 [patent_app_number] => 8/229136 [patent_app_country] => US [patent_app_date] => 1994-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1939 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404466.pdf [firstpage_image] =>[orig_patent_app_number] => 229136 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/229136
Apparatus and method to set and reset a pipeline instruction execution control unit for sequential execution of an instruction interval Apr 17, 1994 Issued
Array ( [id] => 3530673 [patent_doc_number] => 05577243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Reallocation of returned memory blocks sorted in predetermined sizes and addressed by pointer addresses in a free memory list' [patent_app_type] => 1 [patent_app_number] => 8/221420 [patent_app_country] => US [patent_app_date] => 1994-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4202 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/577/05577243.pdf [firstpage_image] =>[orig_patent_app_number] => 221420 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/221420
Reallocation of returned memory blocks sorted in predetermined sizes and addressed by pointer addresses in a free memory list Mar 30, 1994 Issued
Array ( [id] => 3569222 [patent_doc_number] => 05502833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'System and method for management of a predictive split cache for supporting FIFO queues' [patent_app_type] => 1 [patent_app_number] => 8/221140 [patent_app_country] => US [patent_app_date] => 1994-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4822 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502833.pdf [firstpage_image] =>[orig_patent_app_number] => 221140 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/221140
System and method for management of a predictive split cache for supporting FIFO queues Mar 29, 1994 Issued
Array ( [id] => 3428110 [patent_doc_number] => 05394538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Memory selection circuit for selecting one of various memory areas in a memory unit based on the capacity and the starting address of each area' [patent_app_type] => 1 [patent_app_number] => 8/216519 [patent_app_country] => US [patent_app_date] => 1994-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3525 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/394/05394538.pdf [firstpage_image] =>[orig_patent_app_number] => 216519 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/216519
Memory selection circuit for selecting one of various memory areas in a memory unit based on the capacity and the starting address of each area Mar 22, 1994 Issued
Array ( [id] => 3007519 [patent_doc_number] => 05367659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Tag initialization in a controller for two-way set associative cache' [patent_app_type] => 1 [patent_app_number] => 8/216082 [patent_app_country] => US [patent_app_date] => 1994-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5122 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367659.pdf [firstpage_image] =>[orig_patent_app_number] => 216082 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/216082
Tag initialization in a controller for two-way set associative cache Mar 20, 1994 Issued
Array ( [id] => 3433439 [patent_doc_number] => 05390317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Technique to support progressively programmable nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 8/210409 [patent_app_country] => US [patent_app_date] => 1994-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4448 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/390/05390317.pdf [firstpage_image] =>[orig_patent_app_number] => 210409 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/210409
Technique to support progressively programmable nonvolatile memory Mar 17, 1994 Issued
Array ( [id] => 3521683 [patent_doc_number] => 05588131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'System and method for a snooping and snarfing cache in a multiprocessor computer system' [patent_app_type] => 1 [patent_app_number] => 8/208170 [patent_app_country] => US [patent_app_date] => 1994-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3294 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/588/05588131.pdf [firstpage_image] =>[orig_patent_app_number] => 208170 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/208170
System and method for a snooping and snarfing cache in a multiprocessor computer system Mar 8, 1994 Issued
Array ( [id] => 3667346 [patent_doc_number] => 05623628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue' [patent_app_type] => 1 [patent_app_number] => 8/205040 [patent_app_country] => US [patent_app_date] => 1994-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 25162 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623628.pdf [firstpage_image] =>[orig_patent_app_number] => 205040 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/205040
Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue Mar 1, 1994 Issued
Array ( [id] => 3603691 [patent_doc_number] => 05586294 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffer' [patent_app_type] => 1 [patent_app_number] => 8/197368 [patent_app_country] => US [patent_app_date] => 1994-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 12681 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586294.pdf [firstpage_image] =>[orig_patent_app_number] => 197368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/197368
Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffer Feb 15, 1994 Issued
08/187133 SYSTEM FOR CONTROLLING AN INTERNALLY-INSTALLED CACHE MEMORY Jan 26, 1994 Abandoned
Array ( [id] => 3495144 [patent_doc_number] => 05446862 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'System and method for granting or preventing atomic or nonatomic memory access requests to shared memory regions' [patent_app_type] => 1 [patent_app_number] => 8/160363 [patent_app_country] => US [patent_app_date] => 1993-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5945 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446862.pdf [firstpage_image] =>[orig_patent_app_number] => 160363 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/160363
System and method for granting or preventing atomic or nonatomic memory access requests to shared memory regions Nov 28, 1993 Issued
Array ( [id] => 3585579 [patent_doc_number] => 05539893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Multi-level memory and methods for allocating data most likely to be used to the fastest memory level' [patent_app_type] => 1 [patent_app_number] => 8/153520 [patent_app_country] => US [patent_app_date] => 1993-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 13519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539893.pdf [firstpage_image] =>[orig_patent_app_number] => 153520 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/153520
Multi-level memory and methods for allocating data most likely to be used to the fastest memory level Nov 15, 1993 Issued
Array ( [id] => 3537175 [patent_doc_number] => 05504873 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Mass data storage and retrieval system' [patent_app_type] => 1 [patent_app_number] => 8/150810 [patent_app_country] => US [patent_app_date] => 1993-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 13296 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504873.pdf [firstpage_image] =>[orig_patent_app_number] => 150810 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/150810
Mass data storage and retrieval system Nov 11, 1993 Issued
Array ( [id] => 3435525 [patent_doc_number] => 05423019 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Automatic cache flush with readable and writable cache tag memory' [patent_app_type] => 1 [patent_app_number] => 8/143171 [patent_app_country] => US [patent_app_date] => 1993-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 25010 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/423/05423019.pdf [firstpage_image] =>[orig_patent_app_number] => 143171 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/143171
Automatic cache flush with readable and writable cache tag memory Oct 25, 1993 Issued
Array ( [id] => 3456873 [patent_doc_number] => 05388246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Arrangement and method of controlling memory access requests in digital data processing system' [patent_app_type] => 1 [patent_app_number] => 8/136999 [patent_app_country] => US [patent_app_date] => 1993-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3020 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/388/05388246.pdf [firstpage_image] =>[orig_patent_app_number] => 136999 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/136999
Arrangement and method of controlling memory access requests in digital data processing system Oct 17, 1993 Issued
Array ( [id] => 3505620 [patent_doc_number] => 05537570 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Cache with a tag duplicate fault avoidance system and method' [patent_app_type] => 1 [patent_app_number] => 8/136176 [patent_app_country] => US [patent_app_date] => 1993-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2986 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537570.pdf [firstpage_image] =>[orig_patent_app_number] => 136176 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/136176
Cache with a tag duplicate fault avoidance system and method Oct 11, 1993 Issued
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