Search

Frank J. Asta

Examiner (ID: 13044)

Most Active Art Unit
2312
Art Unit(s)
2318, 2752, 2756, 2312
Total Applications
250
Issued Applications
208
Pending Applications
4
Abandoned Applications
38

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3532881 [patent_doc_number] => 05530876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Floppy disk controller incorporating standby signal generating functions for moving the control from an operational mode to a standby mode if predetermined drive conditions exist' [patent_app_type] => 1 [patent_app_number] => 8/131700 [patent_app_country] => US [patent_app_date] => 1993-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1844 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530876.pdf [firstpage_image] =>[orig_patent_app_number] => 131700 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/131700
Floppy disk controller incorporating standby signal generating functions for moving the control from an operational mode to a standby mode if predetermined drive conditions exist Oct 4, 1993 Issued
Array ( [id] => 3575949 [patent_doc_number] => 05526512 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'Dynamic management of snoop granularity for a coherent asynchronous DMA cache' [patent_app_type] => 1 [patent_app_number] => 8/123820 [patent_app_country] => US [patent_app_date] => 1993-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4754 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/526/05526512.pdf [firstpage_image] =>[orig_patent_app_number] => 123820 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/123820
Dynamic management of snoop granularity for a coherent asynchronous DMA cache Sep 19, 1993 Issued
Array ( [id] => 3544604 [patent_doc_number] => 05584029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Data protecting system for an echangeable storage medium comprising power supply control means, medium detection means and medium identifying means' [patent_app_type] => 1 [patent_app_number] => 8/123250 [patent_app_country] => US [patent_app_date] => 1993-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10293 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/584/05584029.pdf [firstpage_image] =>[orig_patent_app_number] => 123250 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/123250
Data protecting system for an echangeable storage medium comprising power supply control means, medium detection means and medium identifying means Sep 19, 1993 Issued
Array ( [id] => 3064796 [patent_doc_number] => 05325511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'True least recently used replacement method and apparatus' [patent_app_type] => 1 [patent_app_number] => 8/121978 [patent_app_country] => US [patent_app_date] => 1993-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9776 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/325/05325511.pdf [firstpage_image] =>[orig_patent_app_number] => 121978 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/121978
True least recently used replacement method and apparatus Sep 13, 1993 Issued
Array ( [id] => 3428082 [patent_doc_number] => 05394536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Stable memory circuit using dual ported VRAM with shift registers in a multiple memory bank setup for high speed data-transfer' [patent_app_type] => 1 [patent_app_number] => 8/118355 [patent_app_country] => US [patent_app_date] => 1993-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2562 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/394/05394536.pdf [firstpage_image] =>[orig_patent_app_number] => 118355 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/118355
Stable memory circuit using dual ported VRAM with shift registers in a multiple memory bank setup for high speed data-transfer Sep 8, 1993 Issued
Array ( [id] => 3439141 [patent_doc_number] => 05455925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Data processing device for maintaining coherency of data stored in main memory, external cache memory and internal cache memory' [patent_app_type] => 1 [patent_app_number] => 8/111731 [patent_app_country] => US [patent_app_date] => 1993-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6602 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455925.pdf [firstpage_image] =>[orig_patent_app_number] => 111731 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/111731
Data processing device for maintaining coherency of data stored in main memory, external cache memory and internal cache memory Aug 22, 1993 Issued
Array ( [id] => 3079541 [patent_doc_number] => 05353429 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-04 [patent_title] => 'Cache memory systems that accesses main memory without wait states during cache misses, using a state machine and address latch in the memory controller' [patent_app_type] => 1 [patent_app_number] => 8/109694 [patent_app_country] => US [patent_app_date] => 1993-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2396 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/353/05353429.pdf [firstpage_image] =>[orig_patent_app_number] => 109694 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/109694
Cache memory systems that accesses main memory without wait states during cache misses, using a state machine and address latch in the memory controller Aug 19, 1993 Issued
Array ( [id] => 3465319 [patent_doc_number] => 05379402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Data processing device for preventing inconsistency of data stored in main memory and cache memory' [patent_app_type] => 1 [patent_app_number] => 8/108284 [patent_app_country] => US [patent_app_date] => 1993-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5497 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379402.pdf [firstpage_image] =>[orig_patent_app_number] => 108284 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/108284
Data processing device for preventing inconsistency of data stored in main memory and cache memory Aug 18, 1993 Issued
Array ( [id] => 3552606 [patent_doc_number] => 05481689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Conversion of internal processor register commands to I/O space addresses' [patent_app_type] => 1 [patent_app_number] => 8/106317 [patent_app_country] => US [patent_app_date] => 1993-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 45352 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481689.pdf [firstpage_image] =>[orig_patent_app_number] => 106317 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/106317
Conversion of internal processor register commands to I/O space addresses Aug 12, 1993 Issued
Array ( [id] => 3473421 [patent_doc_number] => 05392416 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation' [patent_app_type] => 1 [patent_app_number] => 8/103791 [patent_app_country] => US [patent_app_date] => 1993-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 8570 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392416.pdf [firstpage_image] =>[orig_patent_app_number] => 103791 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/103791
Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation Aug 9, 1993 Issued
Array ( [id] => 3024156 [patent_doc_number] => 05333296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'Combined queue for invalidates and return data in multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/103816 [patent_app_country] => US [patent_app_date] => 1993-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 45098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/333/05333296.pdf [firstpage_image] =>[orig_patent_app_number] => 103816 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/103816
Combined queue for invalidates and return data in multiprocessor system Aug 8, 1993 Issued
Array ( [id] => 3616634 [patent_doc_number] => 05579507 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Data transfer control of virtual storage supported by three-level hierarchical storage' [patent_app_type] => 1 [patent_app_number] => 8/102645 [patent_app_country] => US [patent_app_date] => 1993-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8473 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/579/05579507.pdf [firstpage_image] =>[orig_patent_app_number] => 102645 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/102645
Data transfer control of virtual storage supported by three-level hierarchical storage Aug 4, 1993 Issued
Array ( [id] => 3454663 [patent_doc_number] => 05467459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-14 [patent_title] => 'Imaging and graphics processing system' [patent_app_type] => 1 [patent_app_number] => 8/101366 [patent_app_country] => US [patent_app_date] => 1993-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 13203 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/467/05467459.pdf [firstpage_image] =>[orig_patent_app_number] => 101366 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/101366
Imaging and graphics processing system Aug 1, 1993 Issued
Array ( [id] => 3621312 [patent_doc_number] => 05590306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Memory card management system for writing data with usage and recording codes made significant' [patent_app_type] => 1 [patent_app_number] => 8/093640 [patent_app_country] => US [patent_app_date] => 1993-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 19625 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590306.pdf [firstpage_image] =>[orig_patent_app_number] => 093640 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/093640
Memory card management system for writing data with usage and recording codes made significant Jul 19, 1993 Issued
Array ( [id] => 3505720 [patent_doc_number] => 05537576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Expandable memory for a digital signal processor including mapped first and second memory banks forming a continuous and contiguous address space' [patent_app_type] => 1 [patent_app_number] => 8/081670 [patent_app_country] => US [patent_app_date] => 1993-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5275 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537576.pdf [firstpage_image] =>[orig_patent_app_number] => 081670 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/081670
Expandable memory for a digital signal processor including mapped first and second memory banks forming a continuous and contiguous address space Jun 22, 1993 Issued
Array ( [id] => 3544807 [patent_doc_number] => 05584042 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Dynamic I/O data address relocation facility' [patent_app_type] => 1 [patent_app_number] => 8/071160 [patent_app_country] => US [patent_app_date] => 1993-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4488 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/584/05584042.pdf [firstpage_image] =>[orig_patent_app_number] => 071160 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/071160
Dynamic I/O data address relocation facility May 31, 1993 Issued
Array ( [id] => 3058847 [patent_doc_number] => 05287486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'DMA controller using a programmable timer, a transfer counter and an or logic gate to control data transfer interrupts' [patent_app_type] => 1 [patent_app_number] => 8/065511 [patent_app_country] => US [patent_app_date] => 1993-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2229 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/287/05287486.pdf [firstpage_image] =>[orig_patent_app_number] => 065511 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/065511
DMA controller using a programmable timer, a transfer counter and an or logic gate to control data transfer interrupts May 19, 1993 Issued
Array ( [id] => 3529794 [patent_doc_number] => 05506978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Memory apparatus including a shift circuit for shifting a word select signal by a predetermined number of words' [patent_app_type] => 1 [patent_app_number] => 8/062630 [patent_app_country] => US [patent_app_date] => 1993-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6311 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506978.pdf [firstpage_image] =>[orig_patent_app_number] => 062630 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/062630
Memory apparatus including a shift circuit for shifting a word select signal by a predetermined number of words May 17, 1993 Issued
Array ( [id] => 3579569 [patent_doc_number] => 05485597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'A CCD array memory device achieving high speed accessing by writing and reading data through a cache memory' [patent_app_type] => 1 [patent_app_number] => 8/057780 [patent_app_country] => US [patent_app_date] => 1993-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1128 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485597.pdf [firstpage_image] =>[orig_patent_app_number] => 057780 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/057780
A CCD array memory device achieving high speed accessing by writing and reading data through a cache memory May 5, 1993 Issued
Array ( [id] => 3505736 [patent_doc_number] => 05537577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Interleaved memory wherein plural memory means comprising plural banks output data simultaneously while a control unit sequences the addresses in ascending and descending directions' [patent_app_type] => 1 [patent_app_number] => 8/058530 [patent_app_country] => US [patent_app_date] => 1993-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 22097 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537577.pdf [firstpage_image] =>[orig_patent_app_number] => 058530 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/058530
Interleaved memory wherein plural memory means comprising plural banks output data simultaneously while a control unit sequences the addresses in ascending and descending directions May 5, 1993 Issued
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