Search

Frank J. Asta

Examiner (ID: 4289)

Most Active Art Unit
2312
Art Unit(s)
2318, 2756, 2752, 2312
Total Applications
250
Issued Applications
208
Pending Applications
4
Abandoned Applications
38

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5813024 [patent_doc_number] => 20020038894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-04 [patent_title] => 'Fet whose source electrode overhangs gate electrode and its manufacture method' [patent_app_type] => new [patent_app_number] => 09/917894 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4234 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20020038894.pdf [firstpage_image] =>[orig_patent_app_number] => 09917894 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917894
FET whose source electrode overhangs gate electrode and its manufacture method Jul 30, 2001 Issued
Array ( [id] => 6269794 [patent_doc_number] => 20020105091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'DUAL PACKAGE SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/906794 [patent_app_country] => US [patent_app_date] => 2001-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5797 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20020105091.pdf [firstpage_image] =>[orig_patent_app_number] => 09906794 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/906794
Semiconductor device Jul 17, 2001 Issued
Array ( [id] => 1396447 [patent_doc_number] => 06548898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-15 [patent_title] => 'External connection terminal and semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/895330 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 91 [patent_no_of_words] => 12808 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548898.pdf [firstpage_image] =>[orig_patent_app_number] => 09895330 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895330
External connection terminal and semiconductor device Jul 1, 2001 Issued
Array ( [id] => 1404270 [patent_doc_number] => 06541861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Semiconductor device manufacturing method including forming step of SOI structure and semiconductor device having SOI structure' [patent_app_type] => B2 [patent_app_number] => 09/893454 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 4590 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541861.pdf [firstpage_image] =>[orig_patent_app_number] => 09893454 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/893454
Semiconductor device manufacturing method including forming step of SOI structure and semiconductor device having SOI structure Jun 28, 2001 Issued
Array ( [id] => 1419528 [patent_doc_number] => 06525407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Integrated circuit package' [patent_app_type] => B1 [patent_app_number] => 09/895523 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6445 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525407.pdf [firstpage_image] =>[orig_patent_app_number] => 09895523 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895523
Integrated circuit package Jun 28, 2001 Issued
Array ( [id] => 1421529 [patent_doc_number] => 06522021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-18 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/896073 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 7394 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/522/06522021.pdf [firstpage_image] =>[orig_patent_app_number] => 09896073 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/896073
Semiconductor device Jun 27, 2001 Issued
Array ( [id] => 6998491 [patent_doc_number] => 20010052652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Electronic device having fibrous interface' [patent_app_type] => new [patent_app_number] => 09/892244 [patent_app_country] => US [patent_app_date] => 2001-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2782 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20010052652.pdf [firstpage_image] =>[orig_patent_app_number] => 09892244 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/892244
Electronic device having fibrous interface Jun 25, 2001 Issued
Array ( [id] => 7076957 [patent_doc_number] => 20010040294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'Porous dielectric material and electronic devices fabricated therewith' [patent_app_type] => new [patent_app_number] => 09/892234 [patent_app_country] => US [patent_app_date] => 2001-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6920 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20010040294.pdf [firstpage_image] =>[orig_patent_app_number] => 09892234 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/892234
Porous dielectric material and electronic devices fabricated therewith Jun 25, 2001 Issued
Array ( [id] => 7643538 [patent_doc_number] => 06429503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-06 [patent_title] => 'Connection element in an integrated circuit having a layer structure disposed between two conductive structures' [patent_app_type] => B2 [patent_app_number] => 09/888034 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2286 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429503.pdf [firstpage_image] =>[orig_patent_app_number] => 09888034 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/888034
Connection element in an integrated circuit having a layer structure disposed between two conductive structures Jun 21, 2001 Issued
Array ( [id] => 1547617 [patent_doc_number] => 06445077 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Semiconductor chip package' [patent_app_type] => B1 [patent_app_number] => 09/886524 [patent_app_country] => US [patent_app_date] => 2001-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2687 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445077.pdf [firstpage_image] =>[orig_patent_app_number] => 09886524 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/886524
Semiconductor chip package Jun 19, 2001 Issued
Array ( [id] => 1536527 [patent_doc_number] => 06489673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-03 [patent_title] => 'Digital signal processor/known good die packaging using rerouted existing package for test and burn-in carriers' [patent_app_type] => B2 [patent_app_number] => 09/880870 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3492 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489673.pdf [firstpage_image] =>[orig_patent_app_number] => 09880870 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/880870
Digital signal processor/known good die packaging using rerouted existing package for test and burn-in carriers Jun 14, 2001 Issued
Array ( [id] => 6933410 [patent_doc_number] => 20010054754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Surface-mounting type electronic circuit unit suitable for miniaturization and easy to manufacture' [patent_app_type] => new [patent_app_number] => 09/870163 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2049 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20010054754.pdf [firstpage_image] =>[orig_patent_app_number] => 09870163 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870163
Surface-mounting type electronic circuit unit suitable for miniaturization and easy to manufacture May 28, 2001 Abandoned
Array ( [id] => 5798625 [patent_doc_number] => 20020008321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Connection structure' [patent_app_type] => new [patent_app_number] => 09/862503 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2292 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20020008321.pdf [firstpage_image] =>[orig_patent_app_number] => 09862503 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/862503
Connection structure for semiconductor electrode terminals May 22, 2001 Issued
09/807570 Two-dimensional support for semiconductor chips, and a method for producing such a two- dimensional support May 16, 2001 Abandoned
Array ( [id] => 6897465 [patent_doc_number] => 20010045630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Frame for semiconductor package' [patent_app_type] => new [patent_app_number] => 09/850213 [patent_app_country] => US [patent_app_date] => 2001-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2198 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20010045630.pdf [firstpage_image] =>[orig_patent_app_number] => 09850213 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/850213
Frame for semiconductor package including plural lead frames having thin parts or hollows adjacent the terminal roots May 6, 2001 Issued
Array ( [id] => 1168027 [patent_doc_number] => 06759737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Semiconductor package including stacked chips with aligned input/output pads' [patent_app_type] => B2 [patent_app_number] => 09/816599 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4823 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759737.pdf [firstpage_image] =>[orig_patent_app_number] => 09816599 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/816599
Semiconductor package including stacked chips with aligned input/output pads Mar 22, 2001 Issued
Array ( [id] => 5798600 [patent_doc_number] => 20020008306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Optical package with dual interconnect capability' [patent_app_type] => new [patent_app_number] => 09/808654 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4504 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20020008306.pdf [firstpage_image] =>[orig_patent_app_number] => 09808654 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/808654
Optical package with dual interconnect capability Mar 14, 2001 Issued
Array ( [id] => 5856424 [patent_doc_number] => 20020121693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Stacked die package' [patent_app_type] => new [patent_app_number] => 09/734073 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2629 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20020121693.pdf [firstpage_image] =>[orig_patent_app_number] => 09734073 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734073
Stacked die package Dec 10, 2000 Abandoned
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