Frank J. Asta

Array ( [id] => 3567042 [patent_doc_number] => 05500950 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-19 [patent_title] => 'Data processor with speculative data transfer and address-free retry' [patent_app_type] => 1 [patent_app_number] => 8/011024 [patent_app_country] => US [patent_app_date] => 1993-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4983 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/500/05500950.pdf [firstpage_image] =>[orig_patent_app_number] => 011024 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3569208 [patent_doc_number] => 05502832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Associative memory architecture' [patent_app_type] => 1 [patent_app_number] => 8/010600 [patent_app_country] => US [patent_app_date] => 1993-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6985 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502832.pdf [firstpage_image] =>[orig_patent_app_number] => 010600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3564532 [patent_doc_number] => 05493664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Microcomputer that transfers address and control to a debugging routine when an input address is a breakpoint address and a user accessible register for signalling if the breakpoint address is from the cache memory or a main memory' [patent_app_type] => 1 [patent_app_number] => 8/004825 [patent_app_country] => US [patent_app_date] => 1993-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5707 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493664.pdf [firstpage_image] =>[orig_patent_app_number] => 004825 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3495117 [patent_doc_number] => 05446860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Apparatus for determining a computer memory configuration of memory modules using presence detect bits shifted serially into a configuration register' [patent_app_type] => 1 [patent_app_number] => 8/003194 [patent_app_country] => US [patent_app_date] => 1993-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3378 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446860.pdf [firstpage_image] =>[orig_patent_app_number] => 003194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3590423 [patent_doc_number] => 05491809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-13 [patent_title] => 'Smart erase algorithm with secure scheme for flash EPROMs' [patent_app_type] => 1 [patent_app_number] => 8/000764 [patent_app_country] => US [patent_app_date] => 1993-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5845 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/491/05491809.pdf [firstpage_image] =>[orig_patent_app_number] => 000764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3032767 [patent_doc_number] => 05303364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Paged memory controller' [patent_app_type] => 1 [patent_app_number] => 7/999677 [patent_app_country] => US [patent_app_date] => 1992-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 14861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/303/05303364.pdf [firstpage_image] =>[orig_patent_app_number] => 999677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3495103 [patent_doc_number] => 05446859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Register addressing control circuit including a decoder and an index register' [patent_app_type] => 1 [patent_app_number] => 7/995780 [patent_app_country] => US [patent_app_date] => 1992-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1508 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446859.pdf [firstpage_image] =>[orig_patent_app_number] => 995780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3120497 [patent_doc_number] => 05418927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'I/O cache controller containing a buffer memory partitioned into lines accessible by corresponding I/O devices and a directory to track the lines' [patent_app_type] => 1 [patent_app_number] => 7/996501 [patent_app_country] => US [patent_app_date] => 1992-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6787 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418927.pdf [firstpage_image] =>[orig_patent_app_number] => 996501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3527175 [patent_doc_number] => 05487160 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-23 [patent_title] => 'Concurrent image backup for disk storage system' [patent_app_type] => 1 [patent_app_number] => 7/985710 [patent_app_country] => US [patent_app_date] => 1992-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5489 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/487/05487160.pdf [firstpage_image] =>[orig_patent_app_number] => 985710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2915729 [patent_doc_number] => 05249286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'Selectively locking memory locations within a microprocessor\'s on-chip cache' [patent_app_type] => 1 [patent_app_number] => 7/982031 [patent_app_country] => US [patent_app_date] => 1992-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5241 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/249/05249286.pdf [firstpage_image] =>[orig_patent_app_number] => 982031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3435215 [patent_doc_number] => 05459853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Efficient variable-block data storage system employing a staggered fixed-block-architecture array' [patent_app_type] => 1 [patent_app_number] => 7/979740 [patent_app_country] => US [patent_app_date] => 1992-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6953 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459853.pdf [firstpage_image] =>[orig_patent_app_number] => 979740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3122602 [patent_doc_number] => 05465341 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'Verifiable security circuitry for preventing unauthorized access to programmed read only memory' [patent_app_type] => 1 [patent_app_number] => 7/965635 [patent_app_country] => US [patent_app_date] => 1992-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2747 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/465/05465341.pdf [firstpage_image] =>[orig_patent_app_number] => 965635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3435087 [patent_doc_number] => 05459848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Library apparatus with access frequency based addressing' [patent_app_type] => 1 [patent_app_number] => 7/941444 [patent_app_country] => US [patent_app_date] => 1992-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 33 [patent_no_of_words] => 4831 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459848.pdf [firstpage_image] =>[orig_patent_app_number] => 941444 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3440832 [patent_doc_number] => 05463752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Method and system for enhancing the efficiency of communication between multiple direct access storage devices and a storage system controller' [patent_app_type] => 1 [patent_app_number] => 7/949670 [patent_app_country] => US [patent_app_date] => 1992-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2754 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463752.pdf [firstpage_image] =>[orig_patent_app_number] => 949670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3122437 [patent_doc_number] => 05465332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'Selectable 8/16 bit DMA channels for \"ISA\" bus' [patent_app_type] => 1 [patent_app_number] => 7/947680 [patent_app_country] => US [patent_app_date] => 1992-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3540 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/465/05465332.pdf [firstpage_image] =>[orig_patent_app_number] => 947680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3544259 [patent_doc_number] => 05584008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'External storage unit comprising active and inactive storage wherein data is stored in an active storage if in use and archived to an inactive storage when not accessed in predetermined time by the host processor' [patent_app_type] => 1 [patent_app_number] => 7/943580 [patent_app_country] => US [patent_app_date] => 1992-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7930 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/584/05584008.pdf [firstpage_image] =>[orig_patent_app_number] => 943580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3430644 [patent_doc_number] => 05434992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-18 [patent_title] => 'Method and means for dynamically partitioning cache into a global and data type subcache hierarchy from a real time reference trace' [patent_app_type] => 1 [patent_app_number] => 7/940560 [patent_app_country] => US [patent_app_date] => 1992-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8506 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/434/05434992.pdf [firstpage_image] =>[orig_patent_app_number] => 940560 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3122218 [patent_doc_number] => 05408628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Solid state recorder with flexible width data bus utilizing lock mapping and error correction and detection circuits' [patent_app_type] => 1 [patent_app_number] => 7/910720 [patent_app_country] => US [patent_app_date] => 1992-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8510 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/408/05408628.pdf [firstpage_image] =>[orig_patent_app_number] => 910720 [rel_patent_id] =>[rel_patent_doc_number] =>)