
Frank J. Vineis
Examiner (ID: 2880, Phone: (571)270-1547 , Office: P/1786 )
| Most Active Art Unit | 1786 |
| Art Unit(s) | 1781, 1786 |
| Total Applications | 265 |
| Issued Applications | 95 |
| Pending Applications | 23 |
| Abandoned Applications | 150 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1528059
[patent_doc_number] => 06479350
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-12
[patent_title] => 'Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers'
[patent_app_type] => B1
[patent_app_number] => 09/639814
[patent_app_country] => US
[patent_app_date] => 2000-08-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/479/06479350.pdf
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Array
(
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[patent_kind] => B1
[patent_issue_date] => 2002-04-30
[patent_title] => 'Method of breaking electrically conductive traces on substrate into open-circuited state'
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[patent_app_number] => 09/638593
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[patent_app_date] => 2000-08-15
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Array
(
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[patent_doc_number] => 06365430
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-02
[patent_title] => 'Angle cavity resonant photodetector'
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[patent_app_number] => 09/634743
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/634743 | Angle cavity resonant photodetector | Aug 8, 2000 | Issued |
Array
(
[id] => 1564829
[patent_doc_number] => 06338981
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-15
[patent_title] => 'Centrifugally assisted underfill method'
[patent_app_type] => B1
[patent_app_number] => 09/634114
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/634114 | Centrifugally assisted underfill method | Aug 7, 2000 | Issued |
Array
(
[id] => 1565903
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[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Optimization of thermal cycle for the formation of pocket implants'
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Array
(
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[patent_title] => 'Process for planarization a semiconductor substrate'
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Array
(
[id] => 1536180
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[patent_title] => 'Method for fabricating contact of semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/625954 | Method for fabricating contact of semiconductor device | Jul 25, 2000 | Issued |
Array
(
[id] => 1446623
[patent_doc_number] => 06368948
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-09
[patent_title] => 'Method of forming capped copper interconnects with reduced hillocks'
[patent_app_type] => B1
[patent_app_number] => 09/626454
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/626454 | Method of forming capped copper interconnects with reduced hillocks | Jul 25, 2000 | Issued |
Array
(
[id] => 1477693
[patent_doc_number] => 06344402
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-05
[patent_title] => 'Method of dicing workpiece'
[patent_app_type] => B1
[patent_app_number] => 09/624043
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/624043 | Method of dicing workpiece | Jul 23, 2000 | Issued |
Array
(
[id] => 1585365
[patent_doc_number] => 06358779
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-19
[patent_title] => 'Technique for reducing dambar burrs'
[patent_app_type] => B1
[patent_app_number] => 09/614854
[patent_app_country] => US
[patent_app_date] => 2000-07-12
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Array
(
[id] => 1585294
[patent_doc_number] => 06358764
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-19
[patent_title] => 'Semiconductor light emitting device and method of producing same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/614544 | Semiconductor light emitting device and method of producing same | Jul 11, 2000 | Issued |
Array
(
[id] => 1542443
[patent_doc_number] => 06372543
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[patent_issue_date] => 2002-04-16
[patent_title] => 'Wrap-around interconnect for fine pitch ball grid array'
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Array
(
[id] => 1435859
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[patent_title] => 'Semiconductor package and method for making the same'
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Array
(
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[patent_title] => 'Single-layer autorouter'
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Array
(
[id] => 4267701
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[patent_title] => 'Deep trench bottle-shaped etching using Cl2 gas'
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Array
(
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[patent_title] => 'Methods for fabricating microelectronic device interconnects with spun-on glass regions'
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Array
(
[id] => 4270304
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[patent_issue_date] => 2001-06-12
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/518233 | Method for forming an arsenic doped dielectric layer | Mar 2, 2000 | Issued |