Search

Frank J. Vineis

Examiner (ID: 2880, Phone: (571)270-1547 , Office: P/1786 )

Most Active Art Unit
1786
Art Unit(s)
1781, 1786
Total Applications
265
Issued Applications
95
Pending Applications
23
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1528059 [patent_doc_number] => 06479350 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers' [patent_app_type] => B1 [patent_app_number] => 09/639814 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6612 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 612 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479350.pdf [firstpage_image] =>[orig_patent_app_number] => 09639814 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/639814
Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers Aug 16, 2000 Issued
Array ( [id] => 7636596 [patent_doc_number] => 06380059 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method of breaking electrically conductive traces on substrate into open-circuited state' [patent_app_type] => B1 [patent_app_number] => 09/638593 [patent_app_country] => US [patent_app_date] => 2000-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2143 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380059.pdf [firstpage_image] =>[orig_patent_app_number] => 09638593 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638593
Method of breaking electrically conductive traces on substrate into open-circuited state Aug 14, 2000 Issued
Array ( [id] => 1485092 [patent_doc_number] => 06365430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Angle cavity resonant photodetector' [patent_app_type] => B1 [patent_app_number] => 09/634743 [patent_app_country] => US [patent_app_date] => 2000-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3108 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365430.pdf [firstpage_image] =>[orig_patent_app_number] => 09634743 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/634743
Angle cavity resonant photodetector Aug 8, 2000 Issued
Array ( [id] => 1564829 [patent_doc_number] => 06338981 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Centrifugally assisted underfill method' [patent_app_type] => B1 [patent_app_number] => 09/634114 [patent_app_country] => US [patent_app_date] => 2000-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2209 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338981.pdf [firstpage_image] =>[orig_patent_app_number] => 09634114 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/634114
Centrifugally assisted underfill method Aug 7, 2000 Issued
Array ( [id] => 1565903 [patent_doc_number] => 06376341 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Optimization of thermal cycle for the formation of pocket implants' [patent_app_type] => B1 [patent_app_number] => 09/627584 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376341.pdf [firstpage_image] =>[orig_patent_app_number] => 09627584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/627584
Optimization of thermal cycle for the formation of pocket implants Jul 27, 2000 Issued
Array ( [id] => 1459645 [patent_doc_number] => 06391798 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Process for planarization a semiconductor substrate' [patent_app_type] => B1 [patent_app_number] => 09/627084 [patent_app_country] => US [patent_app_date] => 2000-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 4075 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391798.pdf [firstpage_image] =>[orig_patent_app_number] => 09627084 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/627084
Process for planarization a semiconductor substrate Jul 26, 2000 Issued
Array ( [id] => 1536180 [patent_doc_number] => 06337273 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Method for fabricating contact of semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/625954 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3360 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337273.pdf [firstpage_image] =>[orig_patent_app_number] => 09625954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/625954
Method for fabricating contact of semiconductor device Jul 25, 2000 Issued
Array ( [id] => 1446623 [patent_doc_number] => 06368948 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method of forming capped copper interconnects with reduced hillocks' [patent_app_type] => B1 [patent_app_number] => 09/626454 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4491 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368948.pdf [firstpage_image] =>[orig_patent_app_number] => 09626454 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626454
Method of forming capped copper interconnects with reduced hillocks Jul 25, 2000 Issued
Array ( [id] => 1477693 [patent_doc_number] => 06344402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Method of dicing workpiece' [patent_app_type] => B1 [patent_app_number] => 09/624043 [patent_app_country] => US [patent_app_date] => 2000-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 2452 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344402.pdf [firstpage_image] =>[orig_patent_app_number] => 09624043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/624043
Method of dicing workpiece Jul 23, 2000 Issued
Array ( [id] => 1585365 [patent_doc_number] => 06358779 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Technique for reducing dambar burrs' [patent_app_type] => B1 [patent_app_number] => 09/614854 [patent_app_country] => US [patent_app_date] => 2000-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1913 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358779.pdf [firstpage_image] =>[orig_patent_app_number] => 09614854 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/614854
Technique for reducing dambar burrs Jul 11, 2000 Issued
Array ( [id] => 1585294 [patent_doc_number] => 06358764 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Semiconductor light emitting device and method of producing same' [patent_app_type] => B1 [patent_app_number] => 09/614544 [patent_app_country] => US [patent_app_date] => 2000-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 44 [patent_no_of_words] => 12834 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358764.pdf [firstpage_image] =>[orig_patent_app_number] => 09614544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/614544
Semiconductor light emitting device and method of producing same Jul 11, 2000 Issued
Array ( [id] => 1542443 [patent_doc_number] => 06372543 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Wrap-around interconnect for fine pitch ball grid array' [patent_app_type] => B1 [patent_app_number] => 09/565753 [patent_app_country] => US [patent_app_date] => 2000-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372543.pdf [firstpage_image] =>[orig_patent_app_number] => 09565753 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/565753
Wrap-around interconnect for fine pitch ball grid array May 7, 2000 Issued
Array ( [id] => 1435859 [patent_doc_number] => 06355502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Semiconductor package and method for making the same' [patent_app_type] => B1 [patent_app_number] => 09/557344 [patent_app_country] => US [patent_app_date] => 2000-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 3494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355502.pdf [firstpage_image] =>[orig_patent_app_number] => 09557344 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/557344
Semiconductor package and method for making the same Apr 24, 2000 Issued
Array ( [id] => 4326306 [patent_doc_number] => 06319752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Single-layer autorouter' [patent_app_type] => 1 [patent_app_number] => 9/556304 [patent_app_country] => US [patent_app_date] => 2000-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1889 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319752.pdf [firstpage_image] =>[orig_patent_app_number] => 556304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/556304
Single-layer autorouter Apr 23, 2000 Issued
Array ( [id] => 4267701 [patent_doc_number] => 06306772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Deep trench bottle-shaped etching using Cl2 gas' [patent_app_type] => 1 [patent_app_number] => 9/552024 [patent_app_country] => US [patent_app_date] => 2000-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3612 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306772.pdf [firstpage_image] =>[orig_patent_app_number] => 552024 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/552024
Deep trench bottle-shaped etching using Cl2 gas Apr 18, 2000 Issued
Array ( [id] => 1549820 [patent_doc_number] => 06346473 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Methods for fabricating microelectronic device interconnects with spun-on glass regions' [patent_app_type] => B1 [patent_app_number] => 09/550363 [patent_app_country] => US [patent_app_date] => 2000-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 6259 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346473.pdf [firstpage_image] =>[orig_patent_app_number] => 09550363 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/550363
Methods for fabricating microelectronic device interconnects with spun-on glass regions Apr 18, 2000 Issued
Array ( [id] => 4270304 [patent_doc_number] => 06245657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Self-aligned, low contact resistance, via fabrication process' [patent_app_type] => 1 [patent_app_number] => 9/541484 [patent_app_country] => US [patent_app_date] => 2000-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2129 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245657.pdf [firstpage_image] =>[orig_patent_app_number] => 541484 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541484
Self-aligned, low contact resistance, via fabrication process Apr 2, 2000 Issued
Array ( [id] => 4277551 [patent_doc_number] => 06323505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Failure analysis apparatus of semiconductor integrated circuits and methods thereof' [patent_app_type] => 1 [patent_app_number] => 9/541385 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4005 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323505.pdf [firstpage_image] =>[orig_patent_app_number] => 541385 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541385
Failure analysis apparatus of semiconductor integrated circuits and methods thereof Mar 30, 2000 Issued
Array ( [id] => 4407947 [patent_doc_number] => 06309913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Technique for attaching die to leads' [patent_app_type] => 1 [patent_app_number] => 9/537524 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4506 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309913.pdf [firstpage_image] =>[orig_patent_app_number] => 537524 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/537524
Technique for attaching die to leads Mar 28, 2000 Issued
Array ( [id] => 4271799 [patent_doc_number] => 06323137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method for forming an arsenic doped dielectric layer' [patent_app_type] => 1 [patent_app_number] => 9/518233 [patent_app_country] => US [patent_app_date] => 2000-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323137.pdf [firstpage_image] =>[orig_patent_app_number] => 518233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/518233
Method for forming an arsenic doped dielectric layer Mar 2, 2000 Issued
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