Search

Frank J. Vineis

Examiner (ID: 2880, Phone: (571)270-1547 , Office: P/1786 )

Most Active Art Unit
1786
Art Unit(s)
1781, 1786
Total Applications
265
Issued Applications
95
Pending Applications
23
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4394348 [patent_doc_number] => 06297075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method and apparatus for separating semiconductor elements, and mounting method of semiconductor elements' [patent_app_type] => 1 [patent_app_number] => 9/516504 [patent_app_country] => US [patent_app_date] => 2000-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 87 [patent_no_of_words] => 21580 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297075.pdf [firstpage_image] =>[orig_patent_app_number] => 516504 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/516504
Method and apparatus for separating semiconductor elements, and mounting method of semiconductor elements Feb 29, 2000 Issued
Array ( [id] => 4406847 [patent_doc_number] => 06238952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Low-pin-count chip package and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 9/516024 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4073 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238952.pdf [firstpage_image] =>[orig_patent_app_number] => 516024 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/516024
Low-pin-count chip package and manufacturing method thereof Feb 28, 2000 Issued
Array ( [id] => 4275418 [patent_doc_number] => 06307262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Condensed memory matrix' [patent_app_type] => 1 [patent_app_number] => 9/505488 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1931 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307262.pdf [firstpage_image] =>[orig_patent_app_number] => 505488 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/505488
Condensed memory matrix Feb 15, 2000 Issued
Array ( [id] => 4304296 [patent_doc_number] => 06326303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Copper electroless deposition on a titanium-containing surface' [patent_app_type] => 1 [patent_app_number] => 9/503593 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 7394 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326303.pdf [firstpage_image] =>[orig_patent_app_number] => 503593 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/503593
Copper electroless deposition on a titanium-containing surface Feb 10, 2000 Issued
Array ( [id] => 4410979 [patent_doc_number] => 06271588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 9/497684 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 1991 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271588.pdf [firstpage_image] =>[orig_patent_app_number] => 497684 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497684
Semiconductor device and manufacturing method thereof Feb 3, 2000 Issued
Array ( [id] => 4301538 [patent_doc_number] => 06251709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method of manufacturing a cooling structure of a multichip module' [patent_app_type] => 1 [patent_app_number] => 9/498014 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3440 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251709.pdf [firstpage_image] =>[orig_patent_app_number] => 498014 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/498014
Method of manufacturing a cooling structure of a multichip module Feb 3, 2000 Issued
Array ( [id] => 4250441 [patent_doc_number] => 06207552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Forming and filling a recess in interconnect for encapsulation to minimize electromigration' [patent_app_type] => 1 [patent_app_number] => 9/495843 [patent_app_country] => US [patent_app_date] => 2000-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3354 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207552.pdf [firstpage_image] =>[orig_patent_app_number] => 495843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/495843
Forming and filling a recess in interconnect for encapsulation to minimize electromigration Jan 31, 2000 Issued
Array ( [id] => 4297437 [patent_doc_number] => 06236089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'CMOSFET and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/495663 [patent_app_country] => US [patent_app_date] => 2000-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 33 [patent_no_of_words] => 4019 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236089.pdf [firstpage_image] =>[orig_patent_app_number] => 495663 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/495663
CMOSFET and method for fabricating the same Jan 31, 2000 Issued
Array ( [id] => 1536142 [patent_doc_number] => 06337263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Method for improving the quality of metal conductor tracks on semiconductor structures' [patent_app_type] => B1 [patent_app_number] => 09/492654 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1556 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337263.pdf [firstpage_image] =>[orig_patent_app_number] => 09492654 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492654
Method for improving the quality of metal conductor tracks on semiconductor structures Jan 26, 2000 Issued
Array ( [id] => 4380918 [patent_doc_number] => 06294409 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method of forming a constricted-mouth dimple structure on a leadframe die pad' [patent_app_type] => 1 [patent_app_number] => 9/491723 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1972 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294409.pdf [firstpage_image] =>[orig_patent_app_number] => 491723 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/491723
Method of forming a constricted-mouth dimple structure on a leadframe die pad Jan 26, 2000 Issued
Array ( [id] => 4341463 [patent_doc_number] => 06333559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Method/structure for creating aluminum wirebound pad on copper BEOL' [patent_app_type] => 1 [patent_app_number] => 9/487013 [patent_app_country] => US [patent_app_date] => 2000-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3493 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333559.pdf [firstpage_image] =>[orig_patent_app_number] => 487013 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/487013
Method/structure for creating aluminum wirebound pad on copper BEOL Jan 18, 2000 Issued
Array ( [id] => 4267372 [patent_doc_number] => 06306750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Bonding pad structure to prevent inter-metal dielectric cracking and to improve bondability' [patent_app_type] => 1 [patent_app_number] => 9/483934 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1938 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306750.pdf [firstpage_image] =>[orig_patent_app_number] => 483934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/483934
Bonding pad structure to prevent inter-metal dielectric cracking and to improve bondability Jan 17, 2000 Issued
Array ( [id] => 1435911 [patent_doc_number] => 06355554 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Methods of forming filled interconnections in microelectronic devices' [patent_app_type] => B1 [patent_app_number] => 09/482584 [patent_app_country] => US [patent_app_date] => 2000-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 4587 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355554.pdf [firstpage_image] =>[orig_patent_app_number] => 09482584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/482584
Methods of forming filled interconnections in microelectronic devices Jan 12, 2000 Issued
Array ( [id] => 1435864 [patent_doc_number] => 06355507 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Method of forming overmolded chip scale package and resulting product' [patent_app_type] => B1 [patent_app_number] => 09/478386 [patent_app_country] => US [patent_app_date] => 2000-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 5437 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355507.pdf [firstpage_image] =>[orig_patent_app_number] => 09478386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/478386
Method of forming overmolded chip scale package and resulting product Jan 5, 2000 Issued
Array ( [id] => 1435899 [patent_doc_number] => 06355542 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Semiconductor device and manufacturing method' [patent_app_type] => B1 [patent_app_number] => 09/474403 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 39 [patent_no_of_words] => 9537 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355542.pdf [firstpage_image] =>[orig_patent_app_number] => 09474403 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474403
Semiconductor device and manufacturing method Dec 28, 1999 Issued
Array ( [id] => 1549602 [patent_doc_number] => 06346434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Semiconductor device and manufacturing method' [patent_app_type] => B1 [patent_app_number] => 09/474583 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 39 [patent_no_of_words] => 9540 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346434.pdf [firstpage_image] =>[orig_patent_app_number] => 09474583 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474583
Semiconductor device and manufacturing method Dec 28, 1999 Issued
Array ( [id] => 4408340 [patent_doc_number] => 06228684 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Wafer-level package, a method of manufacturing thereof and a method of manufacturing semiconductor devices from such a wafer-level package' [patent_app_type] => 1 [patent_app_number] => 9/472824 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 10218 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228684.pdf [firstpage_image] =>[orig_patent_app_number] => 472824 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472824
Wafer-level package, a method of manufacturing thereof and a method of manufacturing semiconductor devices from such a wafer-level package Dec 27, 1999 Issued
Array ( [id] => 4381667 [patent_doc_number] => 06261939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Pad metallization over active circuitry' [patent_app_type] => 1 [patent_app_number] => 9/472384 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2449 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261939.pdf [firstpage_image] =>[orig_patent_app_number] => 472384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472384
Pad metallization over active circuitry Dec 22, 1999 Issued
Array ( [id] => 4380515 [patent_doc_number] => 06261863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Components with releasable leads and methods of making releasable leads' [patent_app_type] => 1 [patent_app_number] => 9/471973 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5704 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261863.pdf [firstpage_image] =>[orig_patent_app_number] => 471973 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471973
Components with releasable leads and methods of making releasable leads Dec 22, 1999 Issued
Array ( [id] => 4349978 [patent_doc_number] => 06291272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Structure and process for making substrate packages for high frequency application' [patent_app_type] => 1 [patent_app_number] => 9/471563 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3864 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291272.pdf [firstpage_image] =>[orig_patent_app_number] => 471563 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471563
Structure and process for making substrate packages for high frequency application Dec 22, 1999 Issued
Menu