Frank J. Vineis

Array ( [id] => 4408318 [patent_doc_number] => 06228682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Multi-cavity substrate structure for discrete devices' [patent_app_type] => 1 [patent_app_number] => 9/469157 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2210 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228682.pdf [firstpage_image] =>[orig_patent_app_number] => 469157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4318387 [patent_doc_number] => 06248613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Process for fabricating a crack resistant resin encapsulated semiconductor chip package' [patent_app_type] => 1 [patent_app_number] => 9/468684 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 10849 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248613.pdf [firstpage_image] =>[orig_patent_app_number] => 468684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4324382 [patent_doc_number] => 06329222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Interconnect for packaging semiconductor dice and fabricating BGA packages' [patent_app_type] => 1 [patent_app_number] => 9/467643 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 4152 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329222.pdf [firstpage_image] =>[orig_patent_app_number] => 467643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1507291 [patent_doc_number] => 06440786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Boron-carbide and boron rich rhobohedral based transistors and tunnel diodes' [patent_app_type] => B1 [patent_app_number] => 09/465044 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4626 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440786.pdf [firstpage_image] =>[orig_patent_app_number] => 09465044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4360921 [patent_doc_number] => 06201266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/460984 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 5623 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201266.pdf [firstpage_image] =>[orig_patent_app_number] => 460984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7640334 [patent_doc_number] => 06395580 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Backside failure analysis for BGA package' [patent_app_type] => B1 [patent_app_number] => 09/450143 [patent_app_country] => US [patent_app_date] => 1999-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/395/06395580.pdf [firstpage_image] =>[orig_patent_app_number] => 09450143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4269344 [patent_doc_number] => 06245593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Semiconductor device with flat protective adhesive sheet and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/444724 [patent_app_country] => US [patent_app_date] => 1999-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 45 [patent_no_of_words] => 7768 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245593.pdf [firstpage_image] =>[orig_patent_app_number] => 444724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4300279 [patent_doc_number] => 06181010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Semiconductor device and method of manufacturing the same, circuit board and electronic instrument' [patent_app_type] => 1 [patent_app_number] => 9/424484 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4395 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181010.pdf [firstpage_image] =>[orig_patent_app_number] => 424484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4301392 [patent_doc_number] => 06251698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method for making a machined silicon micro-sensor' [patent_app_type] => 1 [patent_app_number] => 9/424223 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 42 [patent_no_of_words] => 5657 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251698.pdf [firstpage_image] =>[orig_patent_app_number] => 424223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4349966 [patent_doc_number] => 06291271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method of making semiconductor chip package' [patent_app_type] => 1 [patent_app_number] => 9/443363 [patent_app_country] => US [patent_app_date] => 1999-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3317 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291271.pdf [firstpage_image] =>[orig_patent_app_number] => 443363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4249222 [patent_doc_number] => 06207467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Multi-chip module with stacked dice' [patent_app_type] => 1 [patent_app_number] => 9/437595 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207467.pdf [firstpage_image] =>[orig_patent_app_number] => 437595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4358455 [patent_doc_number] => 06168970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Ultra high density integrated circuit packages' [patent_app_type] => 1 [patent_app_number] => 9/434534 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 50 [patent_no_of_words] => 10597 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/168/06168970.pdf [firstpage_image] =>[orig_patent_app_number] => 434534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4297791 [patent_doc_number] => 06236112 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Semiconductor device, connecting substrate therefor, and process of manufacturing connecting substrate' [patent_app_type] => 1 [patent_app_number] => 9/434113 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 5352 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236112.pdf [firstpage_image] =>[orig_patent_app_number] => 434113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4416921 [patent_doc_number] => 06194249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Method of assembly stress protection' [patent_app_type] => 1 [patent_app_number] => 9/431133 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1450 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194249.pdf [firstpage_image] =>[orig_patent_app_number] => 431133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4258856 [patent_doc_number] => 06204162 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Production of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/427933 [patent_app_country] => US [patent_app_date] => 1999-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 37 [patent_no_of_words] => 5617 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204162.pdf [firstpage_image] =>[orig_patent_app_number] => 427933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4310782 [patent_doc_number] => 06316354 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Process for removing resist mask of integrated circuit structure which mitigates damage to underlying low dielectric constant silicon oxide dielectric layer' [patent_app_type] => 1 [patent_app_number] => 9/428344 [patent_app_country] => US [patent_app_date] => 1999-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316354.pdf [firstpage_image] =>[orig_patent_app_number] => 428344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4395301 [patent_doc_number] => 06297143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Process for forming a bit-line in a MONOS device' [patent_app_type] => 1 [patent_app_number] => 9/426743 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1786 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297143.pdf [firstpage_image] =>[orig_patent_app_number] => 426743 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7643524 [patent_doc_number] => 06429517 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Semiconductor device and fabrication method thereof' [patent_app_type] => B1 [patent_app_number] => 09/418974 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 3828 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429517.pdf [firstpage_image] =>[orig_patent_app_number] => 09418974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4324988 [patent_doc_number] => 06249045 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Tented plated through-holes and method for fabrication thereof' [patent_app_type] => 1 [patent_app_number] => 9/416284 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2097 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249045.pdf [firstpage_image] =>[orig_patent_app_number] => 416284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4380665 [patent_doc_number] => 06277670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Semiconductor chip package and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 9/416272 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3544 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277670.pdf [firstpage_image] =>[orig_patent_app_number] => 416272 [rel_patent_id] =>[rel_patent_doc_number] =>)