Search

Frank J. Vineis

Examiner (ID: 2880, Phone: (571)270-1547 , Office: P/1786 )

Most Active Art Unit
1786
Art Unit(s)
1781, 1786
Total Applications
265
Issued Applications
95
Pending Applications
23
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4356570 [patent_doc_number] => 06190929 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Methods of forming semiconductor devices and methods of forming field emission displays' [patent_app_type] => 1 [patent_app_number] => 9/360193 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3510 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190929.pdf [firstpage_image] =>[orig_patent_app_number] => 360193 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360193
Methods of forming semiconductor devices and methods of forming field emission displays Jul 22, 1999 Issued
Array ( [id] => 4286283 [patent_doc_number] => 06268225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Fabrication method for integrated passive component' [patent_app_type] => 1 [patent_app_number] => 9/353393 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2090 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268225.pdf [firstpage_image] =>[orig_patent_app_number] => 353393 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/353393
Fabrication method for integrated passive component Jul 14, 1999 Issued
Array ( [id] => 4169590 [patent_doc_number] => 06140220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Dual damascene process and structure with dielectric barrier layer' [patent_app_type] => 1 [patent_app_number] => 9/349843 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2241 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140220.pdf [firstpage_image] =>[orig_patent_app_number] => 349843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/349843
Dual damascene process and structure with dielectric barrier layer Jul 7, 1999 Issued
Array ( [id] => 4405360 [patent_doc_number] => 06271135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method for forming copper-containing metal studs' [patent_app_type] => 1 [patent_app_number] => 9/348553 [patent_app_country] => US [patent_app_date] => 1999-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 4674 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271135.pdf [firstpage_image] =>[orig_patent_app_number] => 348553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348553
Method for forming copper-containing metal studs Jul 6, 1999 Issued
Array ( [id] => 4258032 [patent_doc_number] => 06258610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method analyzing a semiconductor surface using line width metrology with auto-correlation operation' [patent_app_type] => 1 [patent_app_number] => 9/347313 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 55 [patent_no_of_words] => 8182 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258610.pdf [firstpage_image] =>[orig_patent_app_number] => 347313 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/347313
Method analyzing a semiconductor surface using line width metrology with auto-correlation operation Jul 1, 1999 Issued
Array ( [id] => 4145671 [patent_doc_number] => 06060781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/347003 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 38 [patent_no_of_words] => 12119 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060781.pdf [firstpage_image] =>[orig_patent_app_number] => 347003 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/347003
Semiconductor device Jul 1, 1999 Issued
Array ( [id] => 4408155 [patent_doc_number] => 06300185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Polyacrystalline silicon film formation method' [patent_app_type] => 1 [patent_app_number] => 9/345344 [patent_app_country] => US [patent_app_date] => 1999-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3956 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300185.pdf [firstpage_image] =>[orig_patent_app_number] => 345344 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345344
Polyacrystalline silicon film formation method Jun 30, 1999 Issued
Array ( [id] => 4408374 [patent_doc_number] => 06228687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Wafer-level package and methods of fabricating' [patent_app_type] => 1 [patent_app_number] => 9/340513 [patent_app_country] => US [patent_app_date] => 1999-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 26 [patent_no_of_words] => 7091 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228687.pdf [firstpage_image] =>[orig_patent_app_number] => 340513 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340513
Wafer-level package and methods of fabricating Jun 27, 1999 Issued
Array ( [id] => 4168643 [patent_doc_number] => 06140154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Multi-part lead frame with dissimilar materials and method of manufacturing' [patent_app_type] => 1 [patent_app_number] => 9/339284 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6260 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140154.pdf [firstpage_image] =>[orig_patent_app_number] => 339284 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/339284
Multi-part lead frame with dissimilar materials and method of manufacturing Jun 22, 1999 Issued
Array ( [id] => 4361477 [patent_doc_number] => 06201307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Ceramics for wiring boards and method of producing the same' [patent_app_type] => 1 [patent_app_number] => 9/338023 [patent_app_country] => US [patent_app_date] => 1999-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 6975 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201307.pdf [firstpage_image] =>[orig_patent_app_number] => 338023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/338023
Ceramics for wiring boards and method of producing the same Jun 21, 1999 Issued
Array ( [id] => 4409113 [patent_doc_number] => 06228753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method of fabricating a bonding pad structure for improving the bonding pad surface quality' [patent_app_type] => 1 [patent_app_number] => 9/336044 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1282 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228753.pdf [firstpage_image] =>[orig_patent_app_number] => 336044 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/336044
Method of fabricating a bonding pad structure for improving the bonding pad surface quality Jun 17, 1999 Issued
Array ( [id] => 4290193 [patent_doc_number] => 06235625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method of fabricating copper damascene' [patent_app_type] => 1 [patent_app_number] => 9/335553 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 2535 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235625.pdf [firstpage_image] =>[orig_patent_app_number] => 335553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/335553
Method of fabricating copper damascene Jun 17, 1999 Issued
Array ( [id] => 4172928 [patent_doc_number] => 06083825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Method of forming unlanded via hole' [patent_app_type] => 1 [patent_app_number] => 9/329113 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2248 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/083/06083825.pdf [firstpage_image] =>[orig_patent_app_number] => 329113 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/329113
Method of forming unlanded via hole Jun 8, 1999 Issued
Array ( [id] => 4301562 [patent_doc_number] => 06198155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Semiconductor device comprising an integrated circuit provided with a ceramic security coating and method of manufacturing such a device' [patent_app_type] => 1 [patent_app_number] => 9/328253 [patent_app_country] => US [patent_app_date] => 1999-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3386 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198155.pdf [firstpage_image] =>[orig_patent_app_number] => 328253 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/328253
Semiconductor device comprising an integrated circuit provided with a ceramic security coating and method of manufacturing such a device Jun 7, 1999 Issued
Array ( [id] => 4086459 [patent_doc_number] => 06133064 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Flip chip ball grid array package with laminated substrate' [patent_app_type] => 1 [patent_app_number] => 9/322064 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1331 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133064.pdf [firstpage_image] =>[orig_patent_app_number] => 322064 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322064
Flip chip ball grid array package with laminated substrate May 26, 1999 Issued
Array ( [id] => 4195370 [patent_doc_number] => 06153939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Flip-chip semiconductor device with enhanced reliability and manufacturing efficiency, and the method for under filling the same' [patent_app_type] => 1 [patent_app_number] => 9/317354 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1953 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153939.pdf [firstpage_image] =>[orig_patent_app_number] => 317354 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317354
Flip-chip semiconductor device with enhanced reliability and manufacturing efficiency, and the method for under filling the same May 23, 1999 Issued
Array ( [id] => 4408847 [patent_doc_number] => 06265324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Method of manufacturing semiconductor device and mask for forming thin film pattern' [patent_app_type] => 1 [patent_app_number] => 9/315234 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 7219 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265324.pdf [firstpage_image] =>[orig_patent_app_number] => 315234 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315234
Method of manufacturing semiconductor device and mask for forming thin film pattern May 19, 1999 Issued
Array ( [id] => 4182563 [patent_doc_number] => 06159768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Array type multi-chip device and fabrication method therefor' [patent_app_type] => 1 [patent_app_number] => 9/314383 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3217 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/159/06159768.pdf [firstpage_image] =>[orig_patent_app_number] => 314383 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314383
Array type multi-chip device and fabrication method therefor May 18, 1999 Issued
Array ( [id] => 4358442 [patent_doc_number] => 06255185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Two step anneal for controlling resistor tolerance' [patent_app_type] => 1 [patent_app_number] => 9/314513 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3609 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255185.pdf [firstpage_image] =>[orig_patent_app_number] => 314513 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314513
Two step anneal for controlling resistor tolerance May 18, 1999 Issued
Array ( [id] => 4325086 [patent_doc_number] => 06249052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Substrate on chip (SOC) multiple-chip module (MCM) with chip-size-package (CSP) ready configuration' [patent_app_type] => 1 [patent_app_number] => 9/314493 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5349 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249052.pdf [firstpage_image] =>[orig_patent_app_number] => 314493 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314493
Substrate on chip (SOC) multiple-chip module (MCM) with chip-size-package (CSP) ready configuration May 17, 1999 Issued
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