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Frank Niranjan

Examiner (ID: 14361)

Most Active Art Unit
2511
Art Unit(s)
2511, 2818
Total Applications
270
Issued Applications
254
Pending Applications
4
Abandoned Applications
12

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3061330 [patent_doc_number] => 05307286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-26 [patent_title] => 'Method for optimizing automatic place and route layout for full scan circuits' [patent_app_type] => 1 [patent_app_number] => 7/988468 [patent_app_country] => US [patent_app_date] => 1992-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4546 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/307/05307286.pdf [firstpage_image] =>[orig_patent_app_number] => 988468 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/988468
Method for optimizing automatic place and route layout for full scan circuits Dec 9, 1992 Issued
Array ( [id] => 3055155 [patent_doc_number] => 05287290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'Method and apparatus for checking a mask pattern' [patent_app_type] => 1 [patent_app_number] => 7/989459 [patent_app_country] => US [patent_app_date] => 1992-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 4705 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/287/05287290.pdf [firstpage_image] =>[orig_patent_app_number] => 989459 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/989459
Method and apparatus for checking a mask pattern Dec 9, 1992 Issued
Array ( [id] => 2957896 [patent_doc_number] => 05222029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-22 [patent_title] => 'Bitwise implementation mechanism for a circuit design synthesis procedure' [patent_app_type] => 1 [patent_app_number] => 7/988381 [patent_app_country] => US [patent_app_date] => 1992-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4773 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/222/05222029.pdf [firstpage_image] =>[orig_patent_app_number] => 988381 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/988381
Bitwise implementation mechanism for a circuit design synthesis procedure Dec 7, 1992 Issued
Array ( [id] => 3463710 [patent_doc_number] => 05452228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Path delay allocation method in the physical hierarchy' [patent_app_type] => 1 [patent_app_number] => 7/980397 [patent_app_country] => US [patent_app_date] => 1992-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6703 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/452/05452228.pdf [firstpage_image] =>[orig_patent_app_number] => 980397 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/980397
Path delay allocation method in the physical hierarchy Nov 22, 1992 Issued
Array ( [id] => 3435426 [patent_doc_number] => 05416722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-16 [patent_title] => 'System and method for compacting integrated circuit layouts' [patent_app_type] => 1 [patent_app_number] => 7/978558 [patent_app_country] => US [patent_app_date] => 1992-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 6165 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/416/05416722.pdf [firstpage_image] =>[orig_patent_app_number] => 978558 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/978558
System and method for compacting integrated circuit layouts Nov 18, 1992 Issued
Array ( [id] => 3544145 [patent_doc_number] => 05557532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Parameterized generic compiler' [patent_app_type] => 1 [patent_app_number] => 7/975014 [patent_app_country] => US [patent_app_date] => 1992-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 32 [patent_no_of_words] => 8198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/557/05557532.pdf [firstpage_image] =>[orig_patent_app_number] => 975014 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/975014
Parameterized generic compiler Nov 11, 1992 Issued
Array ( [id] => 3622039 [patent_doc_number] => 05566079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Parameterized generic multiplier complier' [patent_app_type] => 1 [patent_app_number] => 7/974457 [patent_app_country] => US [patent_app_date] => 1992-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 36 [patent_no_of_words] => 8493 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/566/05566079.pdf [firstpage_image] =>[orig_patent_app_number] => 974457 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/974457
Parameterized generic multiplier complier Nov 11, 1992 Issued
Array ( [id] => 3040743 [patent_doc_number] => 05343404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-30 [patent_title] => 'Precision digital multimeter and waveform synthesizer for multi-signals with distorted waveforms embedded in noise' [patent_app_type] => 1 [patent_app_number] => 7/975470 [patent_app_country] => US [patent_app_date] => 1992-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 17410 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/343/05343404.pdf [firstpage_image] =>[orig_patent_app_number] => 975470 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/975470
Precision digital multimeter and waveform synthesizer for multi-signals with distorted waveforms embedded in noise Nov 11, 1992 Issued
Array ( [id] => 3113468 [patent_doc_number] => 05448480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Fail-safe operation via controller redundancy for steering the back wheels of a road vehicle' [patent_app_type] => 1 [patent_app_number] => 7/971667 [patent_app_country] => US [patent_app_date] => 1992-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448480.pdf [firstpage_image] =>[orig_patent_app_number] => 971667 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/971667
Fail-safe operation via controller redundancy for steering the back wheels of a road vehicle Nov 3, 1992 Issued
Array ( [id] => 3468077 [patent_doc_number] => 05383124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-17 [patent_title] => 'Process for undercarriage regulation' [patent_app_type] => 1 [patent_app_number] => 7/971686 [patent_app_country] => US [patent_app_date] => 1992-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1718 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/383/05383124.pdf [firstpage_image] =>[orig_patent_app_number] => 971686 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/971686
Process for undercarriage regulation Nov 3, 1992 Issued
Array ( [id] => 3670997 [patent_doc_number] => 05657239 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Timing verification using synchronizers and timing constraints' [patent_app_type] => 1 [patent_app_number] => 7/969933 [patent_app_country] => US [patent_app_date] => 1992-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 37 [patent_no_of_words] => 11766 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/657/05657239.pdf [firstpage_image] =>[orig_patent_app_number] => 969933 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/969933
Timing verification using synchronizers and timing constraints Oct 29, 1992 Issued
Array ( [id] => 3534391 [patent_doc_number] => 05504691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Method and device for tracking down a prespecified subcircuit in an electrical circuit, method for constructing integrated circuit masks using the method' [patent_app_type] => 1 [patent_app_number] => 7/968611 [patent_app_country] => US [patent_app_date] => 1992-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 7074 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504691.pdf [firstpage_image] =>[orig_patent_app_number] => 968611 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/968611
Method and device for tracking down a prespecified subcircuit in an electrical circuit, method for constructing integrated circuit masks using the method Oct 28, 1992 Issued
Array ( [id] => 3602333 [patent_doc_number] => 05521833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Method for programming programmable integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/967857 [patent_app_country] => US [patent_app_date] => 1992-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1434 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/521/05521833.pdf [firstpage_image] =>[orig_patent_app_number] => 967857 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/967857
Method for programming programmable integrated circuits Oct 27, 1992 Issued
Array ( [id] => 3107032 [patent_doc_number] => 05299137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'Behavioral synthesis of circuits including high impedance buffers' [patent_app_type] => 1 [patent_app_number] => 7/970601 [patent_app_country] => US [patent_app_date] => 1992-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3353 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/299/05299137.pdf [firstpage_image] =>[orig_patent_app_number] => 970601 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/970601
Behavioral synthesis of circuits including high impedance buffers Oct 27, 1992 Issued
Array ( [id] => 3467054 [patent_doc_number] => 05473547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-05 [patent_title] => 'Logic synthesizer for engineering changes' [patent_app_type] => 1 [patent_app_number] => 7/966374 [patent_app_country] => US [patent_app_date] => 1992-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4293 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/473/05473547.pdf [firstpage_image] =>[orig_patent_app_number] => 966374 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/966374
Logic synthesizer for engineering changes Oct 25, 1992 Issued
07/965213 METHOD FOR PERFORMING INTEGRATED SECTION-LEVEL AND FULL-CHIP TIMING VERIFICATION FOR CUSTOM MICROPROCESSOR DESIGNS Oct 22, 1992 Abandoned
Array ( [id] => 3497055 [patent_doc_number] => 05475608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'System for designing a placement of a placement element' [patent_app_type] => 1 [patent_app_number] => 7/961546 [patent_app_country] => US [patent_app_date] => 1992-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 13341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475608.pdf [firstpage_image] =>[orig_patent_app_number] => 961546 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/961546
System for designing a placement of a placement element Oct 14, 1992 Issued
07/959178 GAS MOTOR CONTROL Oct 8, 1992 Abandoned
Array ( [id] => 3025073 [patent_doc_number] => 05341309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Apparatus for optimizing hierarchical circuit data base and method for the apparatus' [patent_app_type] => 1 [patent_app_number] => 7/958714 [patent_app_country] => US [patent_app_date] => 1992-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7555 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341309.pdf [firstpage_image] =>[orig_patent_app_number] => 958714 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/958714
Apparatus for optimizing hierarchical circuit data base and method for the apparatus Oct 8, 1992 Issued
Array ( [id] => 2952563 [patent_doc_number] => 05224057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-29 [patent_title] => 'Arrangement method for logic cells in semiconductor IC device' [patent_app_type] => 1 [patent_app_number] => 7/959468 [patent_app_country] => US [patent_app_date] => 1992-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 8200 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/224/05224057.pdf [firstpage_image] =>[orig_patent_app_number] => 959468 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/959468
Arrangement method for logic cells in semiconductor IC device Oct 8, 1992 Issued
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