Search

Frank Niranjan

Examiner (ID: 14361)

Most Active Art Unit
2511
Art Unit(s)
2511, 2818
Total Applications
270
Issued Applications
254
Pending Applications
4
Abandoned Applications
12

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2989119 [patent_doc_number] => 05253182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-12 [patent_title] => 'Method of and apparatus for converting design pattern data to exposure data' [patent_app_type] => 1 [patent_app_number] => 7/653310 [patent_app_country] => US [patent_app_date] => 1991-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6988 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/253/05253182.pdf [firstpage_image] =>[orig_patent_app_number] => 653310 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/653310
Method of and apparatus for converting design pattern data to exposure data Feb 10, 1991 Issued
Array ( [id] => 2985818 [patent_doc_number] => 05225993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Design rule test apparatus for testing if mask pattern satisfies design rule and operation method therefor' [patent_app_type] => 1 [patent_app_number] => 7/655106 [patent_app_country] => US [patent_app_date] => 1991-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 4108 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/225/05225993.pdf [firstpage_image] =>[orig_patent_app_number] => 655106 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/655106
Design rule test apparatus for testing if mask pattern satisfies design rule and operation method therefor Feb 3, 1991 Issued
07/649599 METHOD AND APPARATUS FOR PROVIDING SHORTEST ELAPSED TIME ROUTE INFORMATION TO USERS Jan 31, 1991 Abandoned
07/649014 CONTROL DEVICE FOR AN AUTOMOBILE USING A NEURAL NETWORK AS A CONTROLLER Jan 30, 1991 Abandoned
Array ( [id] => 2908152 [patent_doc_number] => 05245549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-14 [patent_title] => 'Gate addressing system for logic simulation machine' [patent_app_type] => 1 [patent_app_number] => 7/647704 [patent_app_country] => US [patent_app_date] => 1991-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 44 [patent_no_of_words] => 11002 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/245/05245549.pdf [firstpage_image] =>[orig_patent_app_number] => 647704 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/647704
Gate addressing system for logic simulation machine Jan 28, 1991 Issued
Array ( [id] => 3098935 [patent_doc_number] => 05278764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Automatic braking system with proximity detection to a preceding vehicle' [patent_app_type] => 1 [patent_app_number] => 7/646543 [patent_app_country] => US [patent_app_date] => 1991-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4685 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278764.pdf [firstpage_image] =>[orig_patent_app_number] => 646543 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/646543
Automatic braking system with proximity detection to a preceding vehicle Jan 27, 1991 Issued
Array ( [id] => 3003632 [patent_doc_number] => 05367456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Hierarchical control system for automatically guided vehicles' [patent_app_type] => 1 [patent_app_number] => 7/647671 [patent_app_country] => US [patent_app_date] => 1991-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5935 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367456.pdf [firstpage_image] =>[orig_patent_app_number] => 647671 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/647671
Hierarchical control system for automatically guided vehicles Jan 23, 1991 Issued
07/640596 METHOD OF FORMING PATTERN HAVING OPTIONAL ANGLE IN CHARGED PARTICLE EXPOSURE SYSTEM Jan 10, 1991 Abandoned
Array ( [id] => 2893870 [patent_doc_number] => 05268843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-07 [patent_title] => 'Engine misfiring determining device' [patent_app_type] => 1 [patent_app_number] => 7/635370 [patent_app_country] => US [patent_app_date] => 1990-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6511 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/268/05268843.pdf [firstpage_image] =>[orig_patent_app_number] => 635370 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/635370
Engine misfiring determining device Dec 25, 1990 Issued
07/633994 ANTI-LOCK CONTROL METHOD AND APPARATUS FOR AUTOMOTIVE VEHICLES Dec 25, 1990 Abandoned
Array ( [id] => 2922293 [patent_doc_number] => 05237514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-17 [patent_title] => 'Minimizing path delay in a machine by compensation of timing through selective placement and partitioning' [patent_app_type] => 1 [patent_app_number] => 7/632454 [patent_app_country] => US [patent_app_date] => 1990-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 7556 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/237/05237514.pdf [firstpage_image] =>[orig_patent_app_number] => 632454 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/632454
Minimizing path delay in a machine by compensation of timing through selective placement and partitioning Dec 20, 1990 Issued
Array ( [id] => 2944373 [patent_doc_number] => 05197015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'System and method for setting capacitive constraints on synthesized logic circuits' [patent_app_type] => 1 [patent_app_number] => 7/631600 [patent_app_country] => US [patent_app_date] => 1990-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4451 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/197/05197015.pdf [firstpage_image] =>[orig_patent_app_number] => 631600 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/631600
System and method for setting capacitive constraints on synthesized logic circuits Dec 19, 1990 Issued
Array ( [id] => 2977556 [patent_doc_number] => 05202840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Method for partitioning of connected circuit components before placement in one or more integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/630284 [patent_app_country] => US [patent_app_date] => 1990-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4022 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/202/05202840.pdf [firstpage_image] =>[orig_patent_app_number] => 630284 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/630284
Method for partitioning of connected circuit components before placement in one or more integrated circuits Dec 18, 1990 Issued
Array ( [id] => 3003871 [patent_doc_number] => 05367469 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Predictive capacitance layout method for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/627085 [patent_app_country] => US [patent_app_date] => 1990-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2819 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367469.pdf [firstpage_image] =>[orig_patent_app_number] => 627085 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/627085
Predictive capacitance layout method for integrated circuits Dec 12, 1990 Issued
Array ( [id] => 2870092 [patent_doc_number] => 05166888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-24 [patent_title] => 'Fabrication of particle beam masks' [patent_app_type] => 1 [patent_app_number] => 7/626087 [patent_app_country] => US [patent_app_date] => 1990-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 46 [patent_no_of_words] => 4511 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/166/05166888.pdf [firstpage_image] =>[orig_patent_app_number] => 626087 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/626087
Fabrication of particle beam masks Dec 10, 1990 Issued
Array ( [id] => 3028914 [patent_doc_number] => 05303161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Technology independent integrated circuit mask artwork generator' [patent_app_type] => 1 [patent_app_number] => 7/624958 [patent_app_country] => US [patent_app_date] => 1990-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5338 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/303/05303161.pdf [firstpage_image] =>[orig_patent_app_number] => 624958 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/624958
Technology independent integrated circuit mask artwork generator Dec 9, 1990 Issued
Array ( [id] => 2903848 [patent_doc_number] => 05177692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-05 [patent_title] => 'Method and apparatus for processing errors occurring upon division of pattern to be transferred' [patent_app_type] => 1 [patent_app_number] => 7/625271 [patent_app_country] => US [patent_app_date] => 1990-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2778 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/177/05177692.pdf [firstpage_image] =>[orig_patent_app_number] => 625271 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/625271
Method and apparatus for processing errors occurring upon division of pattern to be transferred Dec 9, 1990 Issued
Array ( [id] => 2963842 [patent_doc_number] => 05231589 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-27 [patent_title] => 'Input/output pin assignment method' [patent_app_type] => 1 [patent_app_number] => 7/624565 [patent_app_country] => US [patent_app_date] => 1990-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4663 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/231/05231589.pdf [firstpage_image] =>[orig_patent_app_number] => 624565 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/624565
Input/output pin assignment method Dec 9, 1990 Issued
07/623471 DIAGNOSTIC AIRFLOW MEASUREMENT Dec 6, 1990 Abandoned
Array ( [id] => 2960023 [patent_doc_number] => 05262959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-16 [patent_title] => 'Representation and processing of hierarchical block designs' [patent_app_type] => 1 [patent_app_number] => 7/624007 [patent_app_country] => US [patent_app_date] => 1990-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 4193 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/262/05262959.pdf [firstpage_image] =>[orig_patent_app_number] => 624007 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/624007
Representation and processing of hierarchical block designs Dec 6, 1990 Issued
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