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Frank Niranjan

Examiner (ID: 14361)

Most Active Art Unit
2511
Art Unit(s)
2511, 2818
Total Applications
270
Issued Applications
254
Pending Applications
4
Abandoned Applications
12

Applications

Application numberTitle of the applicationFiling DateStatus
07/401198 ELECTRONIC SYSTEMS AND EMULATION AND TESTING DEVICES, CABLES, SYSTEMS AND METHODS Aug 27, 1989 Abandoned
07/399761 AUTOMATED TRASH MANAGEMENT SYSTEM Aug 27, 1989 Abandoned
Array ( [id] => 3043934 [patent_doc_number] => 05329465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Online valve diagnostic monitoring system' [patent_app_type] => 1 [patent_app_number] => 7/397323 [patent_app_country] => US [patent_app_date] => 1989-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7244 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/329/05329465.pdf [firstpage_image] =>[orig_patent_app_number] => 397323 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/397323
Online valve diagnostic monitoring system Aug 21, 1989 Issued
Array ( [id] => 2796758 [patent_doc_number] => 05155692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Technique for routing conductive paths' [patent_app_type] => 1 [patent_app_number] => 7/396259 [patent_app_country] => US [patent_app_date] => 1989-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2929 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155692.pdf [firstpage_image] =>[orig_patent_app_number] => 396259 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/396259
Technique for routing conductive paths Aug 20, 1989 Issued
Array ( [id] => 2996220 [patent_doc_number] => 05212652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-18 [patent_title] => 'Programmable gate array with improved interconnect structure' [patent_app_type] => 1 [patent_app_number] => 7/394221 [patent_app_country] => US [patent_app_date] => 1989-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 87 [patent_no_of_words] => 24975 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/212/05212652.pdf [firstpage_image] =>[orig_patent_app_number] => 394221 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/394221
Programmable gate array with improved interconnect structure Aug 14, 1989 Issued
Array ( [id] => 2679664 [patent_doc_number] => 05047971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-10 [patent_title] => 'Circuit simulation' [patent_app_type] => 1 [patent_app_number] => 7/394232 [patent_app_country] => US [patent_app_date] => 1989-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 9282 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/047/05047971.pdf [firstpage_image] =>[orig_patent_app_number] => 394232 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/394232
Circuit simulation Aug 14, 1989 Issued
Array ( [id] => 2702736 [patent_doc_number] => 04996644 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-26 [patent_title] => 'Air-fuel ratio control system for use in internal combustion engine' [patent_app_type] => 1 [patent_app_number] => 7/393869 [patent_app_country] => US [patent_app_date] => 1989-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 7733 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/996/04996644.pdf [firstpage_image] =>[orig_patent_app_number] => 393869 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/393869
Air-fuel ratio control system for use in internal combustion engine Aug 13, 1989 Issued
Array ( [id] => 2986821 [patent_doc_number] => 05257201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-26 [patent_title] => 'Method to efficiently reduce the number of connections in a circuit' [patent_app_type] => 1 [patent_app_number] => 7/394247 [patent_app_country] => US [patent_app_date] => 1989-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7795 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/257/05257201.pdf [firstpage_image] =>[orig_patent_app_number] => 394247 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/394247
Method to efficiently reduce the number of connections in a circuit Aug 13, 1989 Issued
07/394264 PROCEDURE FOR INCORPORATING TIMING PARAMETERS IN THE SYNTHESIS OF LOGIC CIRCUIT DESIGNS Aug 6, 1989 Abandoned
07/391672 DATA BASE ACCESS MECHANISM FOR RULES UTILIZED BY A SYNTHESIS PROCEDURE FOR LOGIC CIRCUIT DESIGN Aug 6, 1989 Abandoned
07/391670 RULE STRUCTURE IN A PROCEDURE FOR SYNTHESIS OF LOGIC CIRCUITS Aug 6, 1989 Abandoned
07/391671 RULE STRUCTURE FOR INSERTION OF NEW ELEMENTS IN A CIRCUIT DESIGN SYNTHESIS PROCEDURE Aug 6, 1989 Abandoned
Array ( [id] => 2840003 [patent_doc_number] => 05128868 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'Apparatus for controlling gearshifts in automatic transmission' [patent_app_type] => 1 [patent_app_number] => 7/389851 [patent_app_country] => US [patent_app_date] => 1989-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 17680 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/128/05128868.pdf [firstpage_image] =>[orig_patent_app_number] => 389851 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/389851
Apparatus for controlling gearshifts in automatic transmission Aug 3, 1989 Issued
07/393100 BITWISE IMPLEMENTATION MECHANISM FOR A CIRCUIT DESIGN SYNTHESIS PROCEDURE Aug 2, 1989 Abandoned
Array ( [id] => 2996186 [patent_doc_number] => 05212650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-18 [patent_title] => 'Procedure and data structure for synthesis and transformation of logic circuit designs' [patent_app_type] => 1 [patent_app_number] => 7/393107 [patent_app_country] => US [patent_app_date] => 1989-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3246 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/212/05212650.pdf [firstpage_image] =>[orig_patent_app_number] => 393107 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/393107
Procedure and data structure for synthesis and transformation of logic circuit designs Aug 2, 1989 Issued
Array ( [id] => 2716792 [patent_doc_number] => 05062048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-29 [patent_title] => 'Stretch corrected wireline depth measuring error and log quality indicator method and apparatus' [patent_app_type] => 1 [patent_app_number] => 7/387746 [patent_app_country] => US [patent_app_date] => 1989-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3223 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/062/05062048.pdf [firstpage_image] =>[orig_patent_app_number] => 387746 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/387746
Stretch corrected wireline depth measuring error and log quality indicator method and apparatus Jul 31, 1989 Issued
Array ( [id] => 2606598 [patent_doc_number] => 04965757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-23 [patent_title] => 'Process and device for decoding a code signal' [patent_app_type] => 1 [patent_app_number] => 7/388312 [patent_app_country] => US [patent_app_date] => 1989-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3629 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/965/04965757.pdf [firstpage_image] =>[orig_patent_app_number] => 388312 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/388312
Process and device for decoding a code signal Jul 30, 1989 Issued
Array ( [id] => 2596919 [patent_doc_number] => 04964057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-16 [patent_title] => 'Block placement method' [patent_app_type] => 1 [patent_app_number] => 7/386002 [patent_app_country] => US [patent_app_date] => 1989-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2937 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/964/04964057.pdf [firstpage_image] =>[orig_patent_app_number] => 386002 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/386002
Block placement method Jul 26, 1989 Issued
07/380559 SHRINKABLE BICMOS CIRCUIT LAYOUT Jul 16, 1989 Abandoned
Array ( [id] => 2944390 [patent_doc_number] => 05197016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Integrated silicon-software compiler' [patent_app_type] => 1 [patent_app_number] => 7/380079 [patent_app_country] => US [patent_app_date] => 1989-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7484 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/197/05197016.pdf [firstpage_image] =>[orig_patent_app_number] => 380079 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/380079
Integrated silicon-software compiler Jul 13, 1989 Issued
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