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Frank Niranjan

Examiner (ID: 14361)

Most Active Art Unit
2511
Art Unit(s)
2511, 2818
Total Applications
270
Issued Applications
254
Pending Applications
4
Abandoned Applications
12

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3738672 [patent_doc_number] => 05703788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Configuration management and automated test system ASIC design software' [patent_app_type] => 1 [patent_app_number] => 8/477490 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4155 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703788.pdf [firstpage_image] =>[orig_patent_app_number] => 477490 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/477490
Configuration management and automated test system ASIC design software Jun 6, 1995 Issued
Array ( [id] => 3843227 [patent_doc_number] => 05740071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method and apparatus for selective shape adjustment of hierarchical designs' [patent_app_type] => 1 [patent_app_number] => 8/487814 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2694 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740071.pdf [firstpage_image] =>[orig_patent_app_number] => 487814 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/487814
Method and apparatus for selective shape adjustment of hierarchical designs Jun 6, 1995 Issued
Array ( [id] => 3616474 [patent_doc_number] => 05579497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Devices and systems with parallel logic unit, and methods' [patent_app_type] => 1 [patent_app_number] => 8/484115 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 44 [patent_no_of_words] => 27940 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/579/05579497.pdf [firstpage_image] =>[orig_patent_app_number] => 484115 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/484115
Devices and systems with parallel logic unit, and methods Jun 6, 1995 Issued
Array ( [id] => 3518558 [patent_doc_number] => 05587920 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Computer including a Faraday cage on printed circuit board' [patent_app_type] => 1 [patent_app_number] => 8/485703 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4698 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/587/05587920.pdf [firstpage_image] =>[orig_patent_app_number] => 485703 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/485703
Computer including a Faraday cage on printed circuit board Jun 6, 1995 Issued
Array ( [id] => 3783394 [patent_doc_number] => 05774369 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Computer program product for enabling a computer to remove redundancies using quasi algebraic methods' [patent_app_type] => 1 [patent_app_number] => 8/466917 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6596 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774369.pdf [firstpage_image] =>[orig_patent_app_number] => 466917 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/466917
Computer program product for enabling a computer to remove redundancies using quasi algebraic methods Jun 5, 1995 Issued
Array ( [id] => 3563160 [patent_doc_number] => 05519631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Method of arranging components in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/469375 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2620 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519631.pdf [firstpage_image] =>[orig_patent_app_number] => 469375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/469375
Method of arranging components in semiconductor device Jun 5, 1995 Issued
08/490598 APPARATUS AND METHOD FOR PERFORMING COMPUTATIONS WITH ELECTRICALLY RECONFIGURABLE LOGIC DEVICES Jun 5, 1995 Abandoned
Array ( [id] => 3632546 [patent_doc_number] => 05612891 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Hardware logic emulation system with memory capability' [patent_app_type] => 1 [patent_app_number] => 8/470751 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 83 [patent_no_of_words] => 46978 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612891.pdf [firstpage_image] =>[orig_patent_app_number] => 470751 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/470751
Hardware logic emulation system with memory capability Jun 5, 1995 Issued
08/470185 METHODS FOR PERFORMING SIMULATION USING A HARDWARE LOGIC EMULATION SYSTEM Jun 5, 1995 Abandoned
08/471681 METHODS FOR IMPLEMENTING TRI-STATE NETS IN A LOGIC EMULATION SYSTEM Jun 5, 1995 Abandoned
Array ( [id] => 3671037 [patent_doc_number] => 05657241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Routing methods for use in a logic emulation system' [patent_app_type] => 1 [patent_app_number] => 8/471678 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 83 [patent_no_of_words] => 46957 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/657/05657241.pdf [firstpage_image] =>[orig_patent_app_number] => 471678 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/471678
Routing methods for use in a logic emulation system Jun 5, 1995 Issued
Array ( [id] => 3703376 [patent_doc_number] => 05661662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation' [patent_app_type] => 1 [patent_app_number] => 8/471679 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 83 [patent_no_of_words] => 47008 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661662.pdf [firstpage_image] =>[orig_patent_app_number] => 471679 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/471679
Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation Jun 5, 1995 Issued
Array ( [id] => 3804204 [patent_doc_number] => 05726918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Tool, system and method for dynamic timing analysis in a plural-instance digital system simulation' [patent_app_type] => 1 [patent_app_number] => 8/463881 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4132 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726918.pdf [firstpage_image] =>[orig_patent_app_number] => 463881 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/463881
Tool, system and method for dynamic timing analysis in a plural-instance digital system simulation Jun 4, 1995 Issued
Array ( [id] => 3599880 [patent_doc_number] => 05586044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Array of configurable logic blocks including cascadable lookup tables' [patent_app_type] => 1 [patent_app_number] => 8/461196 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 87 [patent_no_of_words] => 24986 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586044.pdf [firstpage_image] =>[orig_patent_app_number] => 461196 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/461196
Array of configurable logic blocks including cascadable lookup tables Jun 4, 1995 Issued
Array ( [id] => 3898193 [patent_doc_number] => 05724249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'System and method for power management in self-resetting CMOS circuitry' [patent_app_type] => 1 [patent_app_number] => 8/461961 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2827 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724249.pdf [firstpage_image] =>[orig_patent_app_number] => 461961 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/461961
System and method for power management in self-resetting CMOS circuitry Jun 4, 1995 Issued
Array ( [id] => 3471510 [patent_doc_number] => 05469368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Array of configurable logic blocks each including a first lookup table output coupled to selectively replace an output of second lookup with an alternate function output' [patent_app_type] => 1 [patent_app_number] => 8/462934 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 87 [patent_no_of_words] => 24990 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469368.pdf [firstpage_image] =>[orig_patent_app_number] => 462934 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/462934
Array of configurable logic blocks each including a first lookup table output coupled to selectively replace an output of second lookup with an alternate function output Jun 4, 1995 Issued
Array ( [id] => 3697479 [patent_doc_number] => 05691912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Method for entering state flow diagrams using schematic editor programs' [patent_app_type] => 1 [patent_app_number] => 8/465635 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 69 [patent_no_of_words] => 21575 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691912.pdf [firstpage_image] =>[orig_patent_app_number] => 465635 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/465635
Method for entering state flow diagrams using schematic editor programs Jun 4, 1995 Issued
Array ( [id] => 3635940 [patent_doc_number] => 05621650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses' [patent_app_type] => 1 [patent_app_number] => 8/456946 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 16130 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/621/05621650.pdf [firstpage_image] =>[orig_patent_app_number] => 456946 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/456946
Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses May 31, 1995 Issued
Array ( [id] => 3738040 [patent_doc_number] => 05671152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Efficient generation of negative fill shapes for chips and packages' [patent_app_type] => 1 [patent_app_number] => 8/444471 [patent_app_country] => US [patent_app_date] => 1995-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3735 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671152.pdf [firstpage_image] =>[orig_patent_app_number] => 444471 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/444471
Efficient generation of negative fill shapes for chips and packages May 18, 1995 Issued
Array ( [id] => 3726977 [patent_doc_number] => 05617318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Dynamically reconfigurable data processing system' [patent_app_type] => 1 [patent_app_number] => 8/437293 [patent_app_country] => US [patent_app_date] => 1995-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2602 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617318.pdf [firstpage_image] =>[orig_patent_app_number] => 437293 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/437293
Dynamically reconfigurable data processing system May 7, 1995 Issued
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