Search

Frank Sever

Examiner (ID: 2282)

Most Active Art Unit
1306
Art Unit(s)
1306, 1305, 1303, 1801, 2899
Total Applications
1564
Issued Applications
1483
Pending Applications
0
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19748271 [patent_doc_number] => 20250036836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => Method of Generating a 3d Computer-Aided Design (CAD) and System Therefor [patent_app_type] => utility [patent_app_number] => 18/908028 [patent_app_country] => US [patent_app_date] => 2024-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18908028 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/908028
Method for training AI models to generate 3D CAD designs Oct 6, 2024 Issued
Array ( [id] => 19872902 [patent_doc_number] => 12265764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Computerized system and method for 3D CAD design generation [patent_app_type] => utility [patent_app_number] => 18/907937 [patent_app_country] => US [patent_app_date] => 2024-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11832 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18907937 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/907937
Computerized system and method for 3D CAD design generation Oct 6, 2024 Issued
Array ( [id] => 19925081 [patent_doc_number] => 12299365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Method for determining relative energy between systems, and electronic device [patent_app_type] => utility [patent_app_number] => 18/774674 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 4533 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774674 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/774674
Method for determining relative energy between systems, and electronic device Jul 15, 2024 Issued
Array ( [id] => 19499489 [patent_doc_number] => 20240338507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => Hybrid Node Chiplet Stacking Design [patent_app_type] => utility [patent_app_number] => 18/749111 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749111 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749111
Hybrid Node Chiplet Stacking Design Jun 19, 2024 Pending
Array ( [id] => 19482511 [patent_doc_number] => 20240330553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => LIVELOCK DETECTION IN A HARDWARE DESIGN USING FORMAL EVALUATION LOGIC [patent_app_type] => utility [patent_app_number] => 18/742457 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742457 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742457
LIVELOCK DETECTION IN A HARDWARE DESIGN USING FORMAL EVALUATION LOGIC Jun 12, 2024 Pending
Array ( [id] => 19626014 [patent_doc_number] => 12164847 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-10 [patent_title] => Method of generating a 3d computer-aided design (CAD) and system therefor [patent_app_type] => utility [patent_app_number] => 18/742135 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11816 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742135 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742135
Method of generating a 3d computer-aided design (CAD) and system therefor Jun 12, 2024 Issued
Array ( [id] => 19703795 [patent_doc_number] => 12197831 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-14 [patent_title] => Ground motion intensity measure optimization method for seismic response prediction [patent_app_type] => utility [patent_app_number] => 18/739249 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3745 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 697 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739249 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739249
Ground motion intensity measure optimization method for seismic response prediction Jun 9, 2024 Issued
Array ( [id] => 19269223 [patent_doc_number] => 20240212927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => SYSTEM AND METHOD FOR POWERING OR CHARGING RECEIVERS OR DEVICES HAVING SMALL SURFACE AREAS OR VOLUMES [patent_app_type] => utility [patent_app_number] => 18/601426 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601426 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601426
SYSTEM AND METHOD FOR POWERING OR CHARGING RECEIVERS OR DEVICES HAVING SMALL SURFACE AREAS OR VOLUMES Mar 10, 2024 Pending
Array ( [id] => 19251434 [patent_doc_number] => 20240202425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => IMPLEMENTATION OF DEEP NEURAL NETWORKS FOR TESTING AND QUALITY CONTROL IN THE PRODUCTION OF MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/586736 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18586736 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/586736
IMPLEMENTATION OF DEEP NEURAL NETWORKS FOR TESTING AND QUALITY CONTROL IN THE PRODUCTION OF MEMORY DEVICES Feb 25, 2024 Pending
Array ( [id] => 19787570 [patent_doc_number] => 20250061249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => METHOD TO INTEGRATE DIVERSE COMPONENTS FOR SIMULATION OF COMPLEX SYSTEM [patent_app_type] => utility [patent_app_number] => 18/427791 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427791 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/427791
Method to integrate diverse components for simulation of complex system Jan 29, 2024 Issued
Array ( [id] => 19159864 [patent_doc_number] => 20240152571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => DYNAMIC OUTLIER BIAS REDUCTION SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 18/407017 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18407017 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/407017
DYNAMIC OUTLIER BIAS REDUCTION SYSTEM AND METHOD Jan 7, 2024 Pending
Array ( [id] => 20481597 [patent_doc_number] => 12530072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Load adjusted populations of integrated circuit decoupling capacitors [patent_app_type] => utility [patent_app_number] => 18/529178 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529178 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/529178
Load adjusted populations of integrated circuit decoupling capacitors Dec 4, 2023 Issued
Array ( [id] => 19174138 [patent_doc_number] => 20240160112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => MODEL FOR CALCULATING A STOCHASTIC VARIATION IN AN ARBITRARY PATTERN [patent_app_type] => utility [patent_app_number] => 18/527891 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527891 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527891
Model for calculating a stochastic variation in an arbitrary pattern Dec 3, 2023 Issued
Array ( [id] => 19036788 [patent_doc_number] => 20240086603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => DEVICE FOR GENERATING VERIFICATION VECTOR FOR CIRCUIT DESIGN VERIFICATION, CIRCUIT DESIGN SYSTEM, AND REINFORCEMENT LEARNING METHOD OF THE DEVICE AND THE CIRCUIT DESIGN SYSTEM [patent_app_type] => utility [patent_app_number] => 18/511605 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11114 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18511605 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/511605
DEVICE FOR GENERATING VERIFICATION VECTOR FOR CIRCUIT DESIGN VERIFICATION, CIRCUIT DESIGN SYSTEM, AND REINFORCEMENT LEARNING METHOD OF THE DEVICE AND THE CIRCUIT DESIGN SYSTEM Nov 15, 2023 Pending
Array ( [id] => 19022191 [patent_doc_number] => 20240078362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => SYSTEMS AND METHODS FOR MACHINE LEARNING BASED FAST STATIC THERMAL SOLVER [patent_app_type] => utility [patent_app_number] => 18/389212 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18389212 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/389212
Systems and methods for machine learning based fast static thermal solver Nov 12, 2023 Issued
Array ( [id] => 19303909 [patent_doc_number] => 20240232489 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS [patent_app_type] => utility [patent_app_number] => 18/501994 [patent_app_country] => US [patent_app_date] => 2023-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 144522 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18501994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/501994
LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS Nov 3, 2023 Pending
Array ( [id] => 19303909 [patent_doc_number] => 20240232489 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS [patent_app_type] => utility [patent_app_number] => 18/501994 [patent_app_country] => US [patent_app_date] => 2023-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 144522 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18501994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/501994
LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS Nov 2, 2023 Pending
Array ( [id] => 20563777 [patent_doc_number] => 12566384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Method for mask data synthesis with wafer target adjustment [patent_app_type] => utility [patent_app_number] => 18/499955 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 2293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499955 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499955
Method for mask data synthesis with wafer target adjustment Oct 31, 2023 Issued
Array ( [id] => 19963718 [patent_doc_number] => 12333227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-17 [patent_title] => Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QoR) [patent_app_type] => utility [patent_app_number] => 18/489341 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489341 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489341
Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QoR) Oct 17, 2023 Issued
Array ( [id] => 18897486 [patent_doc_number] => 20240012971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => METHOD AND SYSTEM FOR DETERMINING EQUIVALENCE OF DESIGN RULE MANUAL DATA AND DESIGN RULE CHECKING DATA [patent_app_type] => utility [patent_app_number] => 18/473209 [patent_app_country] => US [patent_app_date] => 2023-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18473209 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/473209
Method and system for determining equivalence of design rule manual data and design rule checking data Sep 22, 2023 Issued
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