Search

Frank Sever

Examiner (ID: 2282)

Most Active Art Unit
1306
Art Unit(s)
1306, 1305, 1303, 1801, 2899
Total Applications
1564
Issued Applications
1483
Pending Applications
0
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17018759 [patent_doc_number] => 11088407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => System and method of managing battery cells [patent_app_type] => utility [patent_app_number] => 16/421718 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 9830 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421718 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/421718
System and method of managing battery cells May 23, 2019 Issued
Array ( [id] => 15185953 [patent_doc_number] => 20190363568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => SOLAR WIRELESS COLLECTOR BEACON (DATA HUB) [patent_app_type] => utility [patent_app_number] => 16/420026 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420026 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/420026
Solar wireless collector beacon (data hub) May 21, 2019 Issued
Array ( [id] => 16608282 [patent_doc_number] => 10909289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Livelock detection in a hardware design using formal evaluation logic [patent_app_type] => utility [patent_app_number] => 16/419734 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14141 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16419734 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/419734
Livelock detection in a hardware design using formal evaluation logic May 21, 2019 Issued
Array ( [id] => 16332972 [patent_doc_number] => 20200303938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => PREDICTIVE MANAGEMENT OF BATTERY OPERATION [patent_app_type] => utility [patent_app_number] => 16/417330 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417330 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/417330
Predictive management of battery operation May 19, 2019 Issued
Array ( [id] => 14811479 [patent_doc_number] => 20190272349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => Assessing Performance of a Hardware Design Using Formal Evaluation Logic [patent_app_type] => utility [patent_app_number] => 16/414594 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414594 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414594
Assessing performance of a hardware design using formal evaluation logic May 15, 2019 Issued
Array ( [id] => 16201009 [patent_doc_number] => 10726176 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-28 [patent_title] => Method and apparatus for designing electrical and electronic circuits [patent_app_type] => utility [patent_app_number] => 16/412954 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4868 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412954 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412954
Method and apparatus for designing electrical and electronic circuits May 14, 2019 Issued
Array ( [id] => 16338443 [patent_doc_number] => 10789403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-29 [patent_title] => Grouping and partitioning of properties for logic verification [patent_app_type] => utility [patent_app_number] => 16/411193 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7058 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411193 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411193
Grouping and partitioning of properties for logic verification May 13, 2019 Issued
Array ( [id] => 17955426 [patent_doc_number] => 11481535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Numerical information generation apparatus, numerical information generation method, and program [patent_app_type] => utility [patent_app_number] => 17/054653 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8612 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17054653 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/054653
Numerical information generation apparatus, numerical information generation method, and program May 13, 2019 Issued
Array ( [id] => 16447204 [patent_doc_number] => 10839133 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-17 [patent_title] => Circuit layout similarity metric for semiconductor testsite coverage [patent_app_type] => utility [patent_app_number] => 16/412404 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412404 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412404
Circuit layout similarity metric for semiconductor testsite coverage May 13, 2019 Issued
Array ( [id] => 14782815 [patent_doc_number] => 20190266305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => PLACEMENT-DRIVEN GENERATION OF ERROR DETECTING STRUCTURES IN INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/405467 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5491 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16405467 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/405467
Placement-driven generation of error detecting structures in integrated circuits May 6, 2019 Issued
Array ( [id] => 14751193 [patent_doc_number] => 20190258770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => METHOD FOR IMPROVING CIRCUIT LAYOUT FOR MANUFACTURABILITY [patent_app_type] => utility [patent_app_number] => 16/404326 [patent_app_country] => US [patent_app_date] => 2019-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16404326 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/404326
Method for improving circuit layout for manufacturability May 5, 2019 Issued
Array ( [id] => 19781828 [patent_doc_number] => 12230868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Device for inductive energy transfer into a human body, for example, and use of said device [patent_app_type] => utility [patent_app_number] => 17/051403 [patent_app_country] => US [patent_app_date] => 2019-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3178 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17051403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/051403
Device for inductive energy transfer into a human body, for example, and use of said device May 1, 2019 Issued
Array ( [id] => 14751183 [patent_doc_number] => 20190258765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => CONTROL PATH VERIFICATION OF HARDWARE DESIGN FOR PIPELINED PROCESS [patent_app_type] => utility [patent_app_number] => 16/399218 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399218 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399218
Control path verification of hardware design for pipelined process Apr 29, 2019 Issued
Array ( [id] => 16402896 [patent_doc_number] => 20200343754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => COMMUNICATION ARCHITECTURE BETWEEN EAR BUD DEVICE AND CHARGING DEVICE BASED ON FEWER PINS [patent_app_type] => utility [patent_app_number] => 16/393912 [patent_app_country] => US [patent_app_date] => 2019-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16393912 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/393912
Communication architecture between ear bud device and charging device based on fewer pins Apr 23, 2019 Issued
Array ( [id] => 14688279 [patent_doc_number] => 20190243255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => Method and Apparatus for Fabricating Wafer By Calculating Process Correction Parameters [patent_app_type] => utility [patent_app_number] => 16/385512 [patent_app_country] => US [patent_app_date] => 2019-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16385512 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/385512
Method and apparatus for fabricating wafer by calculating process correction parameters Apr 15, 2019 Issued
Array ( [id] => 15777111 [patent_doc_number] => 20200119573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => Dual Stage Battery Charger [patent_app_type] => utility [patent_app_number] => 16/372752 [patent_app_country] => US [patent_app_date] => 2019-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16372752 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/372752
Dual stage battery charger Apr 1, 2019 Issued
Array ( [id] => 14588875 [patent_doc_number] => 20190222046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => Methods and Devices for Presenting Auxiliary Energy Delivery Indicia on a Display [patent_app_type] => utility [patent_app_number] => 16/363950 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363950 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363950
Methods and devices for presenting auxiliary energy delivery indicia on a display Mar 24, 2019 Issued
Array ( [id] => 17372721 [patent_doc_number] => 20220027773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => NON-ADIABATIC IMPLEMENTATION OF AN ISWAP QUANTUM LOGIC GATE [patent_app_type] => utility [patent_app_number] => 17/433445 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17433445 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/433445
Non-adiabatic implementation of an iSWAP quantum logic gate Mar 4, 2019 Issued
Array ( [id] => 14720297 [patent_doc_number] => 20190251212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => Method for Creating a Netlist [patent_app_type] => utility [patent_app_number] => 16/274951 [patent_app_country] => US [patent_app_date] => 2019-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16274951 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/274951
Method for Creating a Netlist Feb 12, 2019 Abandoned
Array ( [id] => 16323339 [patent_doc_number] => 10783305 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-22 [patent_title] => System, method, and computer program product for handling combinational loops associated with the formal verification of an electronic circuit design [patent_app_type] => utility [patent_app_number] => 16/275280 [patent_app_country] => US [patent_app_date] => 2019-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16275280 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/275280
System, method, and computer program product for handling combinational loops associated with the formal verification of an electronic circuit design Feb 12, 2019 Issued
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