Search

Frank Sever

Examiner (ID: 2282)

Most Active Art Unit
1306
Art Unit(s)
1306, 1305, 1303, 1801, 2899
Total Applications
1564
Issued Applications
1483
Pending Applications
0
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19780291 [patent_doc_number] => 12229324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Security measures for signal paths with tree structures [patent_app_type] => utility [patent_app_number] => 18/371045 [patent_app_country] => US [patent_app_date] => 2023-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4080 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18371045 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/371045
Security measures for signal paths with tree structures Sep 20, 2023 Issued
Array ( [id] => 19084270 [patent_doc_number] => 20240111071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => STRATIGRAPHIC FORWARD MODELING PLATFORM AND METHODS OF USE [patent_app_type] => utility [patent_app_number] => 18/467046 [patent_app_country] => US [patent_app_date] => 2023-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18467046 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/467046
Stratigraphic forward modeling platform and methods of use Sep 13, 2023 Issued
Array ( [id] => 19015169 [patent_doc_number] => 11922102 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-05 [patent_title] => Method to integrate diverse components for simulation of complex system [patent_app_type] => utility [patent_app_number] => 18/451904 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451904 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451904
Method to integrate diverse components for simulation of complex system Aug 17, 2023 Issued
Array ( [id] => 18810330 [patent_doc_number] => 20230384665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => SUB-RESOLUTION ASSIST FEATURES [patent_app_type] => utility [patent_app_number] => 18/447425 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447425 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447425
Sub-resolution assist features Aug 9, 2023 Issued
Array ( [id] => 18742099 [patent_doc_number] => 20230351081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => METHOD AND SYSTEM FOR REDUCING MIGRATION ERRORS [patent_app_type] => utility [patent_app_number] => 18/350129 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350129 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350129
Method and system for reducing migration errors Jul 10, 2023 Issued
Array ( [id] => 19603700 [patent_doc_number] => 20240394580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => AUTOMATIC QUANTUM CIRCUIT CONTROL SKIPS [patent_app_type] => utility [patent_app_number] => 18/201381 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11897 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201381 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201381
AUTOMATIC QUANTUM CIRCUIT CONTROL SKIPS May 23, 2023 Pending
Array ( [id] => 18650172 [patent_doc_number] => 20230296004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => POWER SYSTEM FOR HIGH TEMPERATURE APPLICATIONS WITH RECHARGEABLE ENERGY STORAGE [patent_app_type] => utility [patent_app_number] => 18/201380 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201380 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201380
Power system for high temperature applications with rechargeable energy storage May 23, 2023 Issued
Array ( [id] => 18630608 [patent_doc_number] => 20230289502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => RECOVERY OF A HIERARCHICAL FUNCTIONAL REPRESENTATION OF AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/197869 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197869 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/197869
Recovery of a hierarchical functional representation of an integrated circuit May 15, 2023 Issued
Array ( [id] => 18773109 [patent_doc_number] => 20230367938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => METHOD FOR COMPREHENSIVE LOW POWER SIMULATION COVERAGE [patent_app_type] => utility [patent_app_number] => 18/315076 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315076 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315076
METHOD FOR COMPREHENSIVE LOW POWER SIMULATION COVERAGE May 9, 2023 Pending
Array ( [id] => 19596017 [patent_doc_number] => 12153865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Logic drive based on standard commodity FPGA IC chips [patent_app_type] => utility [patent_app_number] => 18/195324 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 145 [patent_figures_cnt] => 218 [patent_no_of_words] => 144498 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18195324 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/195324
Logic drive based on standard commodity FPGA IC chips May 8, 2023 Issued
Array ( [id] => 18600636 [patent_doc_number] => 20230275439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => MULTI-CELL BATTERY MANAGEMENT DEVICE [patent_app_type] => utility [patent_app_number] => 18/144932 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18144932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/144932
Multi-cell battery management device May 8, 2023 Issued
Array ( [id] => 19413738 [patent_doc_number] => 12079558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => On-the-fly multi-bit flip flop generation [patent_app_type] => utility [patent_app_number] => 18/144685 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18144685 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/144685
On-the-fly multi-bit flip flop generation May 7, 2023 Issued
Array ( [id] => 18554203 [patent_doc_number] => 20230252216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => METHOD AND APPARATUS FOR ELECTROMIGRATION EVALUATION [patent_app_type] => utility [patent_app_number] => 18/302809 [patent_app_country] => US [patent_app_date] => 2023-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302809 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/302809
Method and apparatus for electromigration evaluation Apr 18, 2023 Issued
Array ( [id] => 18711584 [patent_doc_number] => 20230334213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => ANALOG/MIXED-SIGNAL DEFECT SIMULATION AND ANALYSIS METHODOLOGY [patent_app_type] => utility [patent_app_number] => 18/135732 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18135732 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/135732
ANALOG/MIXED-SIGNAL DEFECT SIMULATION AND ANALYSIS METHODOLOGY Apr 16, 2023 Pending
Array ( [id] => 19482520 [patent_doc_number] => 20240330562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => AUTOMATED MULTI-STAGE DESIGN FLOW BASED ON FINAL QUALITY OF RESULT [patent_app_type] => utility [patent_app_number] => 18/192195 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7467 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18192195 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/192195
AUTOMATED MULTI-STAGE DESIGN FLOW BASED ON FINAL QUALITY OF RESULT Mar 28, 2023 Pending
Array ( [id] => 18539734 [patent_doc_number] => 20230244842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS [patent_app_type] => utility [patent_app_number] => 18/126125 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 191465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126125 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/126125
LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS Mar 23, 2023 Pending
Array ( [id] => 18695158 [patent_doc_number] => 20230325578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => METHODS OF DETERMINING AN EFFECT OF ELECTRONIC COMPONENT PLACEMENT ACCURACY ON WIRE LOOPS IN A SEMICONDUCTOR PACKAGE, AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/121100 [patent_app_country] => US [patent_app_date] => 2023-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18121100 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/121100
METHODS OF DETERMINING AN EFFECT OF ELECTRONIC COMPONENT PLACEMENT ACCURACY ON WIRE LOOPS IN A SEMICONDUCTOR PACKAGE, AND RELATED METHODS Mar 13, 2023 Pending
Array ( [id] => 18487222 [patent_doc_number] => 20230214568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => DETECTION METHOD, SYSTEM, ELECTRONIC EQUIPMENT, AND STORAGE MEDIUM OF PRODUCT TEST DATA [patent_app_type] => utility [patent_app_number] => 18/119844 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18119844 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/119844
DETECTION METHOD, SYSTEM, ELECTRONIC EQUIPMENT, AND STORAGE MEDIUM OF PRODUCT TEST DATA Mar 9, 2023 Pending
Array ( [id] => 18847382 [patent_doc_number] => 20230409786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => RECORDING MEDIUM, DESIGN AIDING METHOD, AND INFORMATION PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 18/170777 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170777 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170777
RECORDING MEDIUM, DESIGN AIDING METHOD, AND INFORMATION PROCESSING DEVICE Feb 16, 2023 Pending
Array ( [id] => 18471681 [patent_doc_number] => 20230205967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => THROUGH-SILICON VIA IN INTEGRATED CIRCUIT PACKAGING [patent_app_type] => utility [patent_app_number] => 18/171072 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171072 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/171072
Through-silicon via in integrated circuit packaging Feb 16, 2023 Issued
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