Search

Frank Sever

Examiner (ID: 2282)

Most Active Art Unit
1306
Art Unit(s)
1306, 1305, 1303, 1801, 2899
Total Applications
1564
Issued Applications
1483
Pending Applications
0
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16356988 [patent_doc_number] => 10797507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Wireless charging method, and apparatus and system therefor [patent_app_type] => utility [patent_app_number] => 16/096414 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12564 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16096414 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/096414
Wireless charging method, and apparatus and system therefor Mar 16, 2017 Issued
Array ( [id] => 14797461 [patent_doc_number] => 10401732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Optimization flows of source, mask and projection optics [patent_app_type] => utility [patent_app_number] => 15/451328 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15451328 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/451328
Optimization flows of source, mask and projection optics Mar 5, 2017 Issued
Array ( [id] => 16574348 [patent_doc_number] => 10896272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => High-level synthesis device, high-level synthesis method, and computer readable medium [patent_app_type] => utility [patent_app_number] => 16/470068 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8410 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16470068 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/470068
High-level synthesis device, high-level synthesis method, and computer readable medium Feb 6, 2017 Issued
Array ( [id] => 16921204 [patent_doc_number] => 20210194296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => WIRELESS CHARGING METHOD AND APPARATUS AND SYSTEM THEREFOR [patent_app_type] => utility [patent_app_number] => 16/076079 [patent_app_country] => US [patent_app_date] => 2017-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15284 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16076079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/076079
WIRELESS CHARGING METHOD AND APPARATUS AND SYSTEM THEREFOR Feb 1, 2017 Abandoned
Array ( [id] => 13333127 [patent_doc_number] => 20180218101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => Scoped Simulation For Electrostatic Discharge Protection Verification [patent_app_type] => utility [patent_app_number] => 15/420464 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15420464 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/420464
Scoped simulation for electrostatic discharge protection verification Jan 30, 2017 Issued
Array ( [id] => 14705093 [patent_doc_number] => 10380296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Connecting designs in mixed language environments [patent_app_type] => utility [patent_app_number] => 15/419901 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6276 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15419901 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/419901
Connecting designs in mixed language environments Jan 29, 2017 Issued
Array ( [id] => 11973660 [patent_doc_number] => 20170277813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'METHODS OF RASTERIZING MASK LAYOUT AND METHODS OF FABRICATING PHOTOMASK USING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/418879 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15418879 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/418879
Methods of rasterizing mask layout and methods of fabricating photomask using the same Jan 29, 2017 Issued
Array ( [id] => 13333123 [patent_doc_number] => 20180218099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => TEST CAPABILITY-BASED PRINTED CIRCUIT BOARD ASSEMBLY DESIGN [patent_app_type] => utility [patent_app_number] => 15/419890 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15419890 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/419890
Test capability-based printed circuit board assembly design Jan 29, 2017 Issued
Array ( [id] => 14615253 [patent_doc_number] => 10360329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Multi-cycle signal identification for static timing analysis [patent_app_type] => utility [patent_app_number] => 15/415182 [patent_app_country] => US [patent_app_date] => 2017-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4325 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15415182 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/415182
Multi-cycle signal identification for static timing analysis Jan 24, 2017 Issued
Array ( [id] => 13318903 [patent_doc_number] => 20180210989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => METHOD FOR EFFICIENT LOCALIZED SELF-HEATING ANALYSIS USING LOCATION BASED DELTAT ANALYSIS [patent_app_type] => utility [patent_app_number] => 15/410929 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410929 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/410929
Method for efficient localized self-heating analysis using location based deltat analysis Jan 19, 2017 Issued
Array ( [id] => 13318915 [patent_doc_number] => 20180210995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => ELECTROMIGRATION CHECK IN LAYOUT DESIGN USING COMPILED RULES LIBRARY [patent_app_type] => utility [patent_app_number] => 15/411839 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411839 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/411839
Electromigration check in layout design using compiled rules library Jan 19, 2017 Issued
Array ( [id] => 14265879 [patent_doc_number] => 10282504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Method for improving circuit layout for manufacturability [patent_app_type] => utility [patent_app_number] => 15/411613 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 8350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411613 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/411613
Method for improving circuit layout for manufacturability Jan 19, 2017 Issued
Array ( [id] => 14799033 [patent_doc_number] => 10402521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-03 [patent_title] => Programmable integrated circuits for emulation [patent_app_type] => utility [patent_app_number] => 15/410597 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8761 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410597 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/410597
Programmable integrated circuits for emulation Jan 18, 2017 Issued
Array ( [id] => 12689278 [patent_doc_number] => 20180121592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM, MASK EVALUATION METHOD AND INSPECTION APPARATUS [patent_app_type] => utility [patent_app_number] => 15/410361 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410361 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/410361
Non-transitory computer readable storage medium, mask evaluation method and inspection apparatus Jan 18, 2017 Issued
Array ( [id] => 14458171 [patent_doc_number] => 10325049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Placement-driven generation of error detecting structures in integrated circuits [patent_app_type] => utility [patent_app_number] => 15/408449 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408449 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408449
Placement-driven generation of error detecting structures in integrated circuits Jan 17, 2017 Issued
Array ( [id] => 13304869 [patent_doc_number] => 20180203971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => ADAPTIVE POWER GRID GENERATION [patent_app_type] => utility [patent_app_number] => 15/409152 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15409152 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/409152
Adaptive power grid generation Jan 17, 2017 Issued
Array ( [id] => 13753133 [patent_doc_number] => 10169514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Approximation of resistor-capacitor circuit extraction for thread-safe design changes [patent_app_type] => utility [patent_app_number] => 15/408856 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408856 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408856
Approximation of resistor-capacitor circuit extraction for thread-safe design changes Jan 17, 2017 Issued
Array ( [id] => 11951591 [patent_doc_number] => 20170255742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'METHOD AND SYSTEM FOR VERIFYING LAYOUT OF INTEGRATED CIRCUIT INCLUDING VERTICAL MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 15/407535 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11810 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15407535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/407535
Method and system for verifying layout of integrated circuit including vertical memory cells Jan 16, 2017 Issued
Array ( [id] => 11531385 [patent_doc_number] => 20170091363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'SPICE CIRCUIT MODEL FOR TWINAXIAL CABLE' [patent_app_type] => utility [patent_app_number] => 15/367276 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8198 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367276 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/367276
Spice circuit model for twinaxial cable Dec 1, 2016 Issued
Array ( [id] => 11531386 [patent_doc_number] => 20170091364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'SPICE CIRCUIT MODEL FOR TWINAXIAL CABLE' [patent_app_type] => utility [patent_app_number] => 15/367290 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8185 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367290 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/367290
Spice circuit model for twinaxial cable Dec 1, 2016 Issued
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