Search

Frank Sever

Examiner (ID: 2282)

Most Active Art Unit
1306
Art Unit(s)
1306, 1305, 1303, 1801, 2899
Total Applications
1564
Issued Applications
1483
Pending Applications
0
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14329799 [patent_doc_number] => 10295914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Method and apparatus for fabricating wafer by calculating process correction parameters [patent_app_type] => utility [patent_app_number] => 15/358716 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 7659 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15358716 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/358716
Method and apparatus for fabricating wafer by calculating process correction parameters Nov 21, 2016 Issued
Array ( [id] => 14705113 [patent_doc_number] => 10380306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Layout of standard cells for predetermined function in integrated circuits [patent_app_type] => utility [patent_app_number] => 15/356817 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356817 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/356817
Layout of standard cells for predetermined function in integrated circuits Nov 20, 2016 Issued
Array ( [id] => 14490081 [patent_doc_number] => 10331831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Assessing performance of a hardware design using formal evaluation logic [patent_app_type] => utility [patent_app_number] => 15/340450 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13862 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340450 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340450
Assessing performance of a hardware design using formal evaluation logic Oct 31, 2016 Issued
Array ( [id] => 13707309 [patent_doc_number] => 20170364609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => Livelock Detection in a Hardware Design Using Formal Evaluation Logic [patent_app_type] => utility [patent_app_number] => 15/340638 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340638 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340638
Livelock detection in a hardware design using formal evaluation logic Oct 31, 2016 Issued
Array ( [id] => 14150035 [patent_doc_number] => 10255399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Method, apparatus and system for automatically performing end-to-end channel mapping for an interconnect [patent_app_type] => utility [patent_app_number] => 15/338639 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15338639 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/338639
Method, apparatus and system for automatically performing end-to-end channel mapping for an interconnect Oct 30, 2016 Issued
Array ( [id] => 12689260 [patent_doc_number] => 20180121586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => Coupled-Domains Disturbance Matrix Generation For Fast Simulation Of Wafer Topography Proximity Effects [patent_app_type] => utility [patent_app_number] => 15/339447 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15339447 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/339447
Coupled-domains disturbance matrix generation for fast simulation of wafer topography proximity effects Oct 30, 2016 Issued
Array ( [id] => 11445447 [patent_doc_number] => 20170046468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'CONGESTION AWARE LAYER PROMOTION' [patent_app_type] => utility [patent_app_number] => 15/338630 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4119 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15338630 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/338630
Congestion aware layer promotion Oct 30, 2016 Issued
Array ( [id] => 14092473 [patent_doc_number] => 10242144 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-26 [patent_title] => Methods for minimizing logic overlap on integrated circuits [patent_app_type] => utility [patent_app_number] => 15/338134 [patent_app_country] => US [patent_app_date] => 2016-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13157 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15338134 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/338134
Methods for minimizing logic overlap on integrated circuits Oct 27, 2016 Issued
Array ( [id] => 12187807 [patent_doc_number] => 20180046744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'SYSTEMS AND METHODS FOR CELL ABUTMENT' [patent_app_type] => utility [patent_app_number] => 15/334918 [patent_app_country] => US [patent_app_date] => 2016-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15334918 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/334918
Systems and methods for cell abutment Oct 25, 2016 Issued
Array ( [id] => 13186495 [patent_doc_number] => 10108769 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-23 [patent_title] => Delay modeling for high fan-out nets within circuit designs [patent_app_type] => utility [patent_app_number] => 15/295911 [patent_app_country] => US [patent_app_date] => 2016-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 10072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15295911 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/295911
Delay modeling for high fan-out nets within circuit designs Oct 16, 2016 Issued
Array ( [id] => 13292115 [patent_doc_number] => 10157253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Multi-bit-mapping aware clock gating [patent_app_type] => utility [patent_app_number] => 15/295840 [patent_app_country] => US [patent_app_date] => 2016-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 8847 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15295840 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/295840
Multi-bit-mapping aware clock gating Oct 16, 2016 Issued
Array ( [id] => 13665513 [patent_doc_number] => 10162920 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-25 [patent_title] => System and method for performing out of order name resolution in an electronic design [patent_app_type] => utility [patent_app_number] => 15/294168 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15294168 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/294168
System and method for performing out of order name resolution in an electronic design Oct 13, 2016 Issued
Array ( [id] => 13097413 [patent_doc_number] => 10068047 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-04 [patent_title] => Systems and methods for designing an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/293725 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7307 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15293725 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/293725
Systems and methods for designing an integrated circuit Oct 13, 2016 Issued
Array ( [id] => 14669925 [patent_doc_number] => 10372864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Global routing in circuit design [patent_app_type] => utility [patent_app_number] => 15/293512 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15293512 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/293512
Global routing in circuit design Oct 13, 2016 Issued
Array ( [id] => 13819339 [patent_doc_number] => 10186443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Misalignment/alignment compensation method, semiconductor lithography system, and method of semiconductor patterning [patent_app_type] => utility [patent_app_number] => 15/281083 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4817 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281083 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/281083
Misalignment/alignment compensation method, semiconductor lithography system, and method of semiconductor patterning Sep 29, 2016 Issued
Array ( [id] => 11847472 [patent_doc_number] => 09735029 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-15 [patent_title] => 'Metal fill optimization for self-aligned double patterning' [patent_app_type] => utility [patent_app_number] => 15/273092 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9433 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273092 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273092
Metal fill optimization for self-aligned double patterning Sep 21, 2016 Issued
Array ( [id] => 11385084 [patent_doc_number] => 20170011140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'METHOD AND APPARATUS FOR WORD-LEVEL NETLIST PREPROCESSING AND ANALYSIS USING SAME' [patent_app_type] => utility [patent_app_number] => 15/270958 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8067 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270958 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270958
Method and apparatus for word-level netlist preprocessing and analysis using same Sep 19, 2016 Issued
Array ( [id] => 15639275 [patent_doc_number] => 10592631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Method for performing netlist comparison based on pin connection relationship of components [patent_app_type] => utility [patent_app_number] => 15/778156 [patent_app_country] => US [patent_app_date] => 2016-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3387 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15778156 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/778156
Method for performing netlist comparison based on pin connection relationship of components Aug 25, 2016 Issued
Array ( [id] => 11965316 [patent_doc_number] => 20170269470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'EFFICIENT WAY TO CREATING PROCESS WINDOW ENHANCED PHOTOMASK LAYOUT' [patent_app_type] => utility [patent_app_number] => 15/230356 [patent_app_country] => US [patent_app_date] => 2016-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15230356 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/230356
Efficient way to creating process window enhanced photomask layout Aug 4, 2016 Issued
Array ( [id] => 12180787 [patent_doc_number] => 20180039723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'METHOD OF ADJUSTING METAL LINE PITCH' [patent_app_type] => utility [patent_app_number] => 15/229536 [patent_app_country] => US [patent_app_date] => 2016-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5529 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15229536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/229536
Method of adjusting metal line pitch Aug 4, 2016 Issued
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