Search

Frank Sever

Examiner (ID: 2282)

Most Active Art Unit
1306
Art Unit(s)
1306, 1305, 1303, 1801, 2899
Total Applications
1564
Issued Applications
1483
Pending Applications
0
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12039696 [patent_doc_number] => 09817930 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-14 [patent_title] => 'Method, system, and computer program product for verifying an electronic circuit design with a graph-based proof flow' [patent_app_type] => utility [patent_app_number] => 14/588260 [patent_app_country] => US [patent_app_date] => 2014-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 12102 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14588260 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/588260
Method, system, and computer program product for verifying an electronic circuit design with a graph-based proof flow Dec 30, 2014 Issued
Array ( [id] => 11411002 [patent_doc_number] => 09558307 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-31 [patent_title] => 'System and method for providing a scalable server-implemented regression query environment for remote testing and analysis of a chip-design model' [patent_app_type] => utility [patent_app_number] => 14/587220 [patent_app_country] => US [patent_app_date] => 2014-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14587220 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/587220
System and method for providing a scalable server-implemented regression query environment for remote testing and analysis of a chip-design model Dec 30, 2014 Issued
Array ( [id] => 11466002 [patent_doc_number] => 09582634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Optimizing IC design using retiming and presenting design simulation results as rescheduling optimization' [patent_app_type] => utility [patent_app_number] => 14/583007 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 21151 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583007 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583007
Optimizing IC design using retiming and presenting design simulation results as rescheduling optimization Dec 23, 2014 Issued
Array ( [id] => 10462647 [patent_doc_number] => 20150347662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'CONGESTION AWARE LAYER PROMOTION' [patent_app_type] => utility [patent_app_number] => 14/542824 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4109 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14542824 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/542824
Congestion aware layer promotion Nov 16, 2014 Issued
Array ( [id] => 11345540 [patent_doc_number] => 09529948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Minimizing crossover paths for functional verification of a circuit description' [patent_app_type] => utility [patent_app_number] => 14/529048 [patent_app_country] => US [patent_app_date] => 2014-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5813 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14529048 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/529048
Minimizing crossover paths for functional verification of a circuit description Oct 29, 2014 Issued
Array ( [id] => 10221049 [patent_doc_number] => 20150106042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'COMPUTER-READABLE MEDIUM STORING ANALYSIS-SUPPORT PROGRAM, ANALYSIS SUPPORT METHOD, AND ANALYSIS SUPPORTING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/507046 [patent_app_country] => US [patent_app_date] => 2014-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13537 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14507046 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/507046
COMPUTER-READABLE MEDIUM STORING ANALYSIS-SUPPORT PROGRAM, ANALYSIS SUPPORT METHOD, AND ANALYSIS SUPPORTING DEVICE Oct 5, 2014 Abandoned
Array ( [id] => 13292105 [patent_doc_number] => 10157248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Circuit suitable for generating random bits and circuit for generating random bits [patent_app_type] => utility [patent_app_number] => 15/033630 [patent_app_country] => US [patent_app_date] => 2014-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4023 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15033630 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/033630
Circuit suitable for generating random bits and circuit for generating random bits Sep 16, 2014 Issued
Array ( [id] => 10717018 [patent_doc_number] => 20160063165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'CELL BASED HYBRID RC EXTRACTION' [patent_app_type] => utility [patent_app_number] => 14/471341 [patent_app_country] => US [patent_app_date] => 2014-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6597 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14471341 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/471341
System and method for creating hybrid resistance and capacitance (RC) netlist using three-dimensional RC extraction and 2.5 dimensional RC extraction Aug 27, 2014 Issued
Array ( [id] => 10665114 [patent_doc_number] => 20160011258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'REPLACEMENT METHOD FOR SCAN CELL OF INTEGRATED CIRCUIT, SKEWABLE SCAN CELL AND INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/330146 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330146 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/330146
Replacement method for scan cell of integrated circuit, skewable scan cell and integrated circuit Jul 13, 2014 Issued
Array ( [id] => 11104252 [patent_doc_number] => 20160301222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'Device and Method for Charge Equalization of An Energy Accumulator Arrangement' [patent_app_type] => utility [patent_app_number] => 14/902451 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10030 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14902451 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/902451
Device and method for charge equalization of an energy accumulator arrangement Jun 30, 2014 Issued
Array ( [id] => 10492939 [patent_doc_number] => 20150377961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'SYSTEM AND METHOD FOR TESTING A LOGIC-BASED PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/318976 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 10436 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14318976 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/318976
System and method for testing a logic-based processing device Jun 29, 2014 Issued
Array ( [id] => 10494142 [patent_doc_number] => 20150379164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'MIXED-WIDTH MEMORY TECHNIQUES FOR PROGRAMMABLE LOGIC DEVICES' [patent_app_type] => utility [patent_app_number] => 14/320169 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320169 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320169
Mixed-width memory techniques for programmable logic devices Jun 29, 2014 Issued
Array ( [id] => 11416908 [patent_doc_number] => 09563737 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-07 [patent_title] => 'Method, system, and computer program product for checking or verifying shapes in track patterns for electronic circuit designs' [patent_app_type] => utility [patent_app_number] => 14/318488 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11026 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14318488 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/318488
Method, system, and computer program product for checking or verifying shapes in track patterns for electronic circuit designs Jun 26, 2014 Issued
Array ( [id] => 10462646 [patent_doc_number] => 20150347661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'CONGESTION AWARE LAYER PROMOTION' [patent_app_type] => utility [patent_app_number] => 14/288885 [patent_app_country] => US [patent_app_date] => 2014-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4195 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14288885 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/288885
Congestion aware layer promotion May 27, 2014 Issued
Array ( [id] => 10959246 [patent_doc_number] => 20140362272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'METHOD OF GENERATING PIXEL ARRAY LAYOUT FOR IMAGE SENSOR AND LAYOUT GENERATING SYSTEM USING THE METHOD' [patent_app_type] => utility [patent_app_number] => 14/286040 [patent_app_country] => US [patent_app_date] => 2014-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8527 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14286040 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/286040
Method of generating pixel array layout for image sensor and layout generating system using the method May 22, 2014 Issued
Array ( [id] => 10569482 [patent_doc_number] => 09292652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-22 [patent_title] => 'Generic design rule checking (DRC) test case extraction' [patent_app_type] => utility [patent_app_number] => 14/270528 [patent_app_country] => US [patent_app_date] => 2014-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8820 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14270528 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/270528
Generic design rule checking (DRC) test case extraction May 5, 2014 Issued
Array ( [id] => 10556423 [patent_doc_number] => 09280624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'System and method for efficient statistical timing analysis of cycle time independent tests' [patent_app_type] => utility [patent_app_number] => 14/264199 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4052 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14264199 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/264199
System and method for efficient statistical timing analysis of cycle time independent tests Apr 28, 2014 Issued
Array ( [id] => 10922445 [patent_doc_number] => 20140325465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'CHIP WITH FLEXIBLE PAD SEQUENCE MANIPULATION AND ASSOCIATED METHOD' [patent_app_type] => utility [patent_app_number] => 14/260410 [patent_app_country] => US [patent_app_date] => 2014-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4719 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14260410 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/260410
CHIP WITH FLEXIBLE PAD SEQUENCE MANIPULATION AND ASSOCIATED METHOD Apr 23, 2014 Abandoned
Array ( [id] => 11285747 [patent_doc_number] => 09501602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Electromigration-aware layout generation' [patent_app_type] => utility [patent_app_number] => 14/255325 [patent_app_country] => US [patent_app_date] => 2014-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 9419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255325 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/255325
Electromigration-aware layout generation Apr 16, 2014 Issued
Array ( [id] => 11246901 [patent_doc_number] => 09472952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Battery module, method for managing supply of electrical power by the battery module, and power supply device having the battery module' [patent_app_type] => utility [patent_app_number] => 14/252938 [patent_app_country] => US [patent_app_date] => 2014-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5724 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14252938 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/252938
Battery module, method for managing supply of electrical power by the battery module, and power supply device having the battery module Apr 14, 2014 Issued
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