Search

Frank Sever

Examiner (ID: 2282)

Most Active Art Unit
1306
Art Unit(s)
1306, 1305, 1303, 1801, 2899
Total Applications
1564
Issued Applications
1483
Pending Applications
0
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9057011 [patent_doc_number] => 20130254725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'EXTRACTION OF IMAGING PARAMETERS FOR COMPUTATIONAL LITHOGRAPHY USING A DATA WEIGHTING ALGORITHM' [patent_app_type] => utility [patent_app_number] => 13/849301 [patent_app_country] => US [patent_app_date] => 2013-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4420 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13849301 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/849301
EXTRACTION OF IMAGING PARAMETERS FOR COMPUTATIONAL LITHOGRAPHY USING A DATA WEIGHTING ALGORITHM Mar 21, 2013 Abandoned
Array ( [id] => 13920159 [patent_doc_number] => 10204203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Pattern-based power-and-ground (PG) routing and via creation [patent_app_type] => utility [patent_app_number] => 13/849427 [patent_app_country] => US [patent_app_date] => 2013-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4444 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13849427 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/849427
Pattern-based power-and-ground (PG) routing and via creation Mar 21, 2013 Issued
Array ( [id] => 9746621 [patent_doc_number] => 20140282340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD FOR PROVISIONING DECOUPLING CAPACITANCE IN AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/837565 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13837565 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/837565
Method for provisioning decoupling capacitance in an integrated circuit Mar 14, 2013 Issued
Array ( [id] => 9954532 [patent_doc_number] => 09003346 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-04-07 [patent_title] => 'Stability improvements for timing-driven place and route' [patent_app_type] => utility [patent_app_number] => 13/801791 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 22092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13801791 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/801791
Stability improvements for timing-driven place and route Mar 12, 2013 Issued
Array ( [id] => 9986621 [patent_doc_number] => 09032358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-12 [patent_title] => 'Integrated circuit floorplan for compact clock distribution' [patent_app_type] => utility [patent_app_number] => 13/787647 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4553 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787647 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/787647
Integrated circuit floorplan for compact clock distribution Mar 5, 2013 Issued
Array ( [id] => 8886761 [patent_doc_number] => 20130159945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'LAYOUT DECOMPOSITION FOR DOUBLE PATTERNING LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 13/766349 [patent_app_country] => US [patent_app_date] => 2013-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9342 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13766349 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/766349
Layout decomposition for double patterning lithography Feb 12, 2013 Issued
Array ( [id] => 8855666 [patent_doc_number] => 20130145341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'SEMICONDUCTOR CIRCUIT DESIGN SUPPORT TECHNIQUE' [patent_app_type] => utility [patent_app_number] => 13/757340 [patent_app_country] => US [patent_app_date] => 2013-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11024 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13757340 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/757340
SEMICONDUCTOR CIRCUIT DESIGN SUPPORT TECHNIQUE Jan 31, 2013 Abandoned
Array ( [id] => 11802327 [patent_doc_number] => 09543223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Method and apparatus for fabricating wafer by calculating process correction parameters' [patent_app_type] => utility [patent_app_number] => 13/749740 [patent_app_country] => US [patent_app_date] => 2013-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 7833 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13749740 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/749740
Method and apparatus for fabricating wafer by calculating process correction parameters Jan 24, 2013 Issued
Array ( [id] => 9891725 [patent_doc_number] => 08978000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Performance-driven and gradient-aware dummy insertion for gradient-sensitive array' [patent_app_type] => utility [patent_app_number] => 13/727691 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727691 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/727691
Performance-driven and gradient-aware dummy insertion for gradient-sensitive array Dec 26, 2012 Issued
Array ( [id] => 11193226 [patent_doc_number] => 09424043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-23 [patent_title] => 'Forward-flow selection' [patent_app_type] => utility [patent_app_number] => 13/727837 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727837 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/727837
Forward-flow selection Dec 26, 2012 Issued
Array ( [id] => 9532666 [patent_doc_number] => 08756553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-17 [patent_title] => 'Computer product, design support method, design support apparatus, and manufacture method' [patent_app_type] => utility [patent_app_number] => 13/726211 [patent_app_country] => US [patent_app_date] => 2012-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 29 [patent_no_of_words] => 17507 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13726211 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/726211
Computer product, design support method, design support apparatus, and manufacture method Dec 22, 2012 Issued
Array ( [id] => 9564048 [patent_doc_number] => 20140181761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'IDENTIFYING CIRCUIT ELEMENTS FOR SELECTIVE INCLUSION IN SPEED-PUSH PROCESSING IN AN INTEGRATED CIRCUIT, AND RELATED CIRCUIT SYSTEMS, APPARATUS, AND COMPUTER-READABLE MEDIA' [patent_app_type] => utility [patent_app_number] => 13/723919 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5623 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13723919 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/723919
IDENTIFYING CIRCUIT ELEMENTS FOR SELECTIVE INCLUSION IN SPEED-PUSH PROCESSING IN AN INTEGRATED CIRCUIT, AND RELATED CIRCUIT SYSTEMS, APPARATUS, AND COMPUTER-READABLE MEDIA Dec 20, 2012 Abandoned
Array ( [id] => 9564055 [patent_doc_number] => 20140181768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'AUTOMATED PERFORMANCE VERIFICATION FOR INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 13/723279 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4200 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13723279 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/723279
AUTOMATED PERFORMANCE VERIFICATION FOR INTEGRATED CIRCUIT DESIGN Dec 20, 2012 Abandoned
Array ( [id] => 9564067 [patent_doc_number] => 20140181780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'ELECTROMIGRATION ANALYSIS FOR STANDARD CELL BASED DESIGNS' [patent_app_type] => utility [patent_app_number] => 13/725121 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13725121 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/725121
ELECTROMIGRATION ANALYSIS FOR STANDARD CELL BASED DESIGNS Dec 20, 2012 Abandoned
Array ( [id] => 9548893 [patent_doc_number] => 20140173541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'Method and Apparatus for Verifying Debugging of Integrated Circuit Designs' [patent_app_type] => utility [patent_app_number] => 13/719570 [patent_app_country] => US [patent_app_date] => 2012-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6419 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13719570 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/719570
Method and Apparatus for Verifying Debugging of Integrated Circuit Designs Dec 18, 2012 Abandoned
Array ( [id] => 9548891 [patent_doc_number] => 20140173539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'Method and Apparatus for Isolating and/or Debugging Defects in Integrated Circuit Designs' [patent_app_type] => utility [patent_app_number] => 13/719559 [patent_app_country] => US [patent_app_date] => 2012-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5942 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13719559 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/719559
Method and Apparatus for Isolating and/or Debugging Defects in Integrated Circuit Designs Dec 18, 2012 Abandoned
Array ( [id] => 8886768 [patent_doc_number] => 20130159952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'COMBINING MULTIPLE TIMING MODES OF INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/716501 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6306 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13716501 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/716501
COMBINING MULTIPLE TIMING MODES OF INTEGRATED CIRCUIT Dec 16, 2012 Abandoned
Array ( [id] => 11204652 [patent_doc_number] => 09434266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Method for monitoring and optimising the operation of a charging terminal for an electric vehicle and charging terminal for implementing said method' [patent_app_type] => utility [patent_app_number] => 14/351698 [patent_app_country] => US [patent_app_date] => 2012-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3693 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14351698 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/351698
Method for monitoring and optimising the operation of a charging terminal for an electric vehicle and charging terminal for implementing said method Dec 13, 2012 Issued
Array ( [id] => 9507233 [patent_doc_number] => 08745562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Method of on-board wiring' [patent_app_type] => utility [patent_app_number] => 13/705229 [patent_app_country] => US [patent_app_date] => 2012-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 7103 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13705229 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/705229
Method of on-board wiring Dec 4, 2012 Issued
Array ( [id] => 9242369 [patent_doc_number] => 08607175 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-10 [patent_title] => 'Identifying logic blocks in a synthesized logic design that have specified inputs' [patent_app_type] => utility [patent_app_number] => 13/693127 [patent_app_country] => US [patent_app_date] => 2012-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5294 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13693127 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/693127
Identifying logic blocks in a synthesized logic design that have specified inputs Dec 3, 2012 Issued
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