
Frank Sever
Examiner (ID: 2282)
| Most Active Art Unit | 1306 |
| Art Unit(s) | 1306, 1305, 1303, 1801, 2899 |
| Total Applications | 1564 |
| Issued Applications | 1483 |
| Pending Applications | 0 |
| Abandoned Applications | 81 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9057011
[patent_doc_number] => 20130254725
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-26
[patent_title] => 'EXTRACTION OF IMAGING PARAMETERS FOR COMPUTATIONAL LITHOGRAPHY USING A DATA WEIGHTING ALGORITHM'
[patent_app_type] => utility
[patent_app_number] => 13/849301
[patent_app_country] => US
[patent_app_date] => 2013-03-22
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/849301 | EXTRACTION OF IMAGING PARAMETERS FOR COMPUTATIONAL LITHOGRAPHY USING A DATA WEIGHTING ALGORITHM | Mar 21, 2013 | Abandoned |
Array
(
[id] => 13920159
[patent_doc_number] => 10204203
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-12
[patent_title] => Pattern-based power-and-ground (PG) routing and via creation
[patent_app_type] => utility
[patent_app_number] => 13/849427
[patent_app_country] => US
[patent_app_date] => 2013-03-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/849427 | Pattern-based power-and-ground (PG) routing and via creation | Mar 21, 2013 | Issued |
Array
(
[id] => 9746621
[patent_doc_number] => 20140282340
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'METHOD FOR PROVISIONING DECOUPLING CAPACITANCE IN AN INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/837565
[patent_app_country] => US
[patent_app_date] => 2013-03-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/837565 | Method for provisioning decoupling capacitance in an integrated circuit | Mar 14, 2013 | Issued |
Array
(
[id] => 9954532
[patent_doc_number] => 09003346
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-04-07
[patent_title] => 'Stability improvements for timing-driven place and route'
[patent_app_type] => utility
[patent_app_number] => 13/801791
[patent_app_country] => US
[patent_app_date] => 2013-03-13
[patent_effective_date] => 0000-00-00
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Array
(
[id] => 9986621
[patent_doc_number] => 09032358
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[patent_kind] => B2
[patent_issue_date] => 2015-05-12
[patent_title] => 'Integrated circuit floorplan for compact clock distribution'
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Array
(
[id] => 8886761
[patent_doc_number] => 20130159945
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-20
[patent_title] => 'LAYOUT DECOMPOSITION FOR DOUBLE PATTERNING LITHOGRAPHY'
[patent_app_type] => utility
[patent_app_number] => 13/766349
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/766349 | Layout decomposition for double patterning lithography | Feb 12, 2013 | Issued |
Array
(
[id] => 8855666
[patent_doc_number] => 20130145341
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[patent_title] => 'SEMICONDUCTOR CIRCUIT DESIGN SUPPORT TECHNIQUE'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/757340 | SEMICONDUCTOR CIRCUIT DESIGN SUPPORT TECHNIQUE | Jan 31, 2013 | Abandoned |
Array
(
[id] => 11802327
[patent_doc_number] => 09543223
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[patent_kind] => B2
[patent_issue_date] => 2017-01-10
[patent_title] => 'Method and apparatus for fabricating wafer by calculating process correction parameters'
[patent_app_type] => utility
[patent_app_number] => 13/749740
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[patent_app_date] => 2013-01-25
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/749740 | Method and apparatus for fabricating wafer by calculating process correction parameters | Jan 24, 2013 | Issued |
Array
(
[id] => 9891725
[patent_doc_number] => 08978000
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-10
[patent_title] => 'Performance-driven and gradient-aware dummy insertion for gradient-sensitive array'
[patent_app_type] => utility
[patent_app_number] => 13/727691
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/727691 | Performance-driven and gradient-aware dummy insertion for gradient-sensitive array | Dec 26, 2012 | Issued |
Array
(
[id] => 11193226
[patent_doc_number] => 09424043
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[patent_issue_date] => 2016-08-23
[patent_title] => 'Forward-flow selection'
[patent_app_type] => utility
[patent_app_number] => 13/727837
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[patent_app_date] => 2012-12-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/727837 | Forward-flow selection | Dec 26, 2012 | Issued |
Array
(
[id] => 9532666
[patent_doc_number] => 08756553
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-17
[patent_title] => 'Computer product, design support method, design support apparatus, and manufacture method'
[patent_app_type] => utility
[patent_app_number] => 13/726211
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/726211 | Computer product, design support method, design support apparatus, and manufacture method | Dec 22, 2012 | Issued |
Array
(
[id] => 9564048
[patent_doc_number] => 20140181761
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-26
[patent_title] => 'IDENTIFYING CIRCUIT ELEMENTS FOR SELECTIVE INCLUSION IN SPEED-PUSH PROCESSING IN AN INTEGRATED CIRCUIT, AND RELATED CIRCUIT SYSTEMS, APPARATUS, AND COMPUTER-READABLE MEDIA'
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Array
(
[id] => 9564055
[patent_doc_number] => 20140181768
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[patent_issue_date] => 2014-06-26
[patent_title] => 'AUTOMATED PERFORMANCE VERIFICATION FOR INTEGRATED CIRCUIT DESIGN'
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Array
(
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[patent_doc_number] => 20140181780
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[patent_issue_date] => 2014-06-26
[patent_title] => 'ELECTROMIGRATION ANALYSIS FOR STANDARD CELL BASED DESIGNS'
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Array
(
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Array
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/351698 | Method for monitoring and optimising the operation of a charging terminal for an electric vehicle and charging terminal for implementing said method | Dec 13, 2012 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/693127 | Identifying logic blocks in a synthesized logic design that have specified inputs | Dec 3, 2012 | Issued |