Search

Frank Sever

Examiner (ID: 2282)

Most Active Art Unit
1306
Art Unit(s)
1306, 1305, 1303, 1801, 2899
Total Applications
1564
Issued Applications
1483
Pending Applications
0
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18165493 [patent_doc_number] => 20230032092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => AUGMENTED RELIABILITY MODELS FOR DESIGN AND MANUFACTURING [patent_app_type] => utility [patent_app_number] => 17/957152 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17957152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/957152
Augmented reliability models for design and manufacturing Sep 29, 2022 Issued
Array ( [id] => 20507352 [patent_doc_number] => 12541629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Graph representation of a circuit simulation waveform [patent_app_type] => utility [patent_app_number] => 17/955117 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17955117 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/955117
Graph representation of a circuit simulation waveform Sep 27, 2022 Issued
Array ( [id] => 20359292 [patent_doc_number] => 12475291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Method for generating analog schematic diagram based on building block classification and reinforcement learning [patent_app_type] => utility [patent_app_number] => 17/941406 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17941406 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/941406
Method for generating analog schematic diagram based on building block classification and reinforcement learning Sep 8, 2022 Issued
Array ( [id] => 18407886 [patent_doc_number] => 20230169239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => DEVICE AND METHOD FOR IMPROVING SIMULATOR PARAMETER [patent_app_type] => utility [patent_app_number] => 17/941448 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17941448 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/941448
DEVICE AND METHOD FOR IMPROVING SIMULATOR PARAMETER Sep 8, 2022 Pending
Array ( [id] => 19053461 [patent_doc_number] => 20240095430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => Power Prediction Systems, Circuitry and Methods [patent_app_type] => utility [patent_app_number] => 17/902810 [patent_app_country] => US [patent_app_date] => 2022-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8101 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902810 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/902810
Power Prediction Systems, Circuitry and Methods Sep 2, 2022 Pending
Array ( [id] => 18158093 [patent_doc_number] => 20230024684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => COMPUTING PARASITIC VALUES FOR SEMICONDUCTOR DESIGNS [patent_app_type] => utility [patent_app_number] => 17/889376 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889376 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889376
Computing parasitic values for semiconductor designs Aug 15, 2022 Issued
Array ( [id] => 18438714 [patent_doc_number] => 20230186009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => COMPUTING PARASITIC VALUES FOR SEMICONDUCTOR DESIGNS [patent_app_type] => utility [patent_app_number] => 17/889370 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11368 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889370
Computing parasitic values for semiconductor designs Aug 15, 2022 Issued
Array ( [id] => 20595634 [patent_doc_number] => 12579353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Computing parasitic values for semiconductor designs [patent_app_type] => utility [patent_app_number] => 17/889373 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 6606 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889373 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889373
Computing parasitic values for semiconductor designs Aug 15, 2022 Issued
Array ( [id] => 18974283 [patent_doc_number] => 20240054375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => CIRCUIT REDUCTION FOR EXPONENTIALS OF PAULI OPERATORS [patent_app_type] => utility [patent_app_number] => 17/819681 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819681 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/819681
Circuit reduction for exponentials of Pauli operators Aug 14, 2022 Issued
Array ( [id] => 18975784 [patent_doc_number] => 20240055876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => HIGH-VOLTAGE BATTERY DISCONNECT METHOD AND MOTOR VEHICLE USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/887011 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887011 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/887011
High-voltage battery disconnect method and motor vehicle using the same Aug 11, 2022 Issued
Array ( [id] => 18756469 [patent_doc_number] => 20230359919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => BUSES FOR MODULAR QUBIT DEVICES [patent_app_type] => utility [patent_app_number] => 17/819535 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/819535
BUSES FOR MODULAR QUBIT DEVICES Aug 11, 2022 Pending
Array ( [id] => 20190103 [patent_doc_number] => 12401232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Wireless power systems with frequency-shift-keying communications [patent_app_type] => utility [patent_app_number] => 17/883401 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883401 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883401
Wireless power systems with frequency-shift-keying communications Aug 7, 2022 Issued
Array ( [id] => 18713011 [patent_doc_number] => 20230335644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => Gates of Hybrid-Fin Devices [patent_app_type] => utility [patent_app_number] => 17/815898 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815898 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815898
Gates of hybrid-fin devices Jul 27, 2022 Issued
Array ( [id] => 18164661 [patent_doc_number] => 20230031257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => SYSTEM AND METHOD FOR WIRELESS POWER TRANSMISSION [patent_app_type] => utility [patent_app_number] => 17/876415 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876415 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876415
System and method for wireless power transmission Jul 27, 2022 Issued
Array ( [id] => 20388447 [patent_doc_number] => 12488175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Methods and systems to determine parasitics for semiconductor or flat panel display fabrication [patent_app_type] => utility [patent_app_number] => 17/871893 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 5669 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871893 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/871893
Methods and systems to determine parasitics for semiconductor or flat panel display fabrication Jul 21, 2022 Issued
Array ( [id] => 18297303 [patent_doc_number] => 20230106989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => METHOD OF VERIFYING SEMICONDUCTOR DEVICE, METHOD OF DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME, AND SYSTEM PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/851842 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10241 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851842 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851842
Method of verifying semiconductor device, method of designing and manufacturing semiconductor device using the same, and system performing the same Jun 27, 2022 Issued
Array ( [id] => 18847386 [patent_doc_number] => 20230409790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => MACHINE LEARNING TECHNIQUES FOR CIRCUIT DESIGN DEBUGGING [patent_app_type] => utility [patent_app_number] => 17/846181 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846181 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/846181
Machine learning techniques for circuit design debugging Jun 21, 2022 Issued
Array ( [id] => 20610246 [patent_doc_number] => 12585848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Machine learning techniques for circuit design verification [patent_app_type] => utility [patent_app_number] => 17/845784 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845784 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/845784
Machine learning techniques for circuit design verification Jun 20, 2022 Issued
Array ( [id] => 19228662 [patent_doc_number] => 12008299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Buffer insertion method and device, storage medium, and electronic device [patent_app_type] => utility [patent_app_number] => 17/806975 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806975
Buffer insertion method and device, storage medium, and electronic device Jun 14, 2022 Issued
Array ( [id] => 18832953 [patent_doc_number] => 20230401480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => HARDWARE ACCELERATION OF MACHINE LEARNING DESIGNS [patent_app_type] => utility [patent_app_number] => 17/806906 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806906
Hardware acceleration of machine learning designs Jun 13, 2022 Issued
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