Search

Frantz Coby

Examiner (ID: 9410, Phone: (571)272-4017 , Office: P/2164 )

Most Active Art Unit
2454
Art Unit(s)
2771, 2787, 2459, 2171, 2454, 2456, 2307, 4174, 2156, 2164, 2161, 771
Total Applications
1615
Issued Applications
1397
Pending Applications
114
Abandoned Applications
133

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13226359 [patent_doc_number] => 10126954 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-13 [patent_title] => Chipset and server system using the same [patent_app_type] => utility [patent_app_number] => 16/124377 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3870 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124377 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/124377
Chipset and server system using the same Sep 6, 2018 Issued
Array ( [id] => 16186143 [patent_doc_number] => 10719476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Apparatus and methods for providing a reconfigurable bidirectional front-end interface [patent_app_type] => utility [patent_app_number] => 16/058251 [patent_app_country] => US [patent_app_date] => 2018-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6140 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16058251 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/058251
Apparatus and methods for providing a reconfigurable bidirectional front-end interface Aug 7, 2018 Issued
Array ( [id] => 15412617 [patent_doc_number] => 20200026631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => DYNAMIC I/O MONITORING AND TUNING [patent_app_type] => utility [patent_app_number] => 16/041777 [patent_app_country] => US [patent_app_date] => 2018-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16041777 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/041777
DYNAMIC I/O MONITORING AND TUNING Jul 20, 2018 Abandoned
Array ( [id] => 15412547 [patent_doc_number] => 20200026596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => I/O RECOVERY AND DIAGNOSTICS [patent_app_type] => utility [patent_app_number] => 16/041776 [patent_app_country] => US [patent_app_date] => 2018-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16041776 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/041776
I/O RECOVERY AND DIAGNOSTICS Jul 20, 2018 Abandoned
Array ( [id] => 14997907 [patent_doc_number] => 20190317911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => GENERAL PURPOSE INPUT OUTPUT TRIGGERED INTERFACE MESSAGE [patent_app_type] => utility [patent_app_number] => 16/037802 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037802 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/037802
GENERAL PURPOSE INPUT OUTPUT TRIGGERED INTERFACE MESSAGE Jul 16, 2018 Abandoned
Array ( [id] => 14379481 [patent_doc_number] => 20190163653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => APPARATUSES AND METHODS INCLUDING MEMORY COMMANDS FOR SEMICONDUCTOR MEMORIES [patent_app_type] => utility [patent_app_number] => 16/035452 [patent_app_country] => US [patent_app_date] => 2018-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035452 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/035452
Apparatuses and methods including memory commands for semiconductor memories Jul 12, 2018 Issued
Array ( [id] => 15313327 [patent_doc_number] => 10521369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-31 [patent_title] => Host device with multi-path layer configured for per-process data reduction control [patent_app_type] => utility [patent_app_number] => 16/034603 [patent_app_country] => US [patent_app_date] => 2018-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10867 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16034603 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/034603
Host device with multi-path layer configured for per-process data reduction control Jul 12, 2018 Issued
Array ( [id] => 16846340 [patent_doc_number] => 11018444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Multi-mode and/or multi-speed non-volatile memory (NVM) express (NVMe) over fabrics (NVMe-of) device [patent_app_type] => utility [patent_app_number] => 16/033141 [patent_app_country] => US [patent_app_date] => 2018-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 10500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033141 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/033141
Multi-mode and/or multi-speed non-volatile memory (NVM) express (NVMe) over fabrics (NVMe-of) device Jul 10, 2018 Issued
Array ( [id] => 16944201 [patent_doc_number] => 11056452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Interface bus for inter-die communication in a multi-chip package over high density interconnects [patent_app_type] => utility [patent_app_number] => 16/023724 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9235 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16023724 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/023724
Interface bus for inter-die communication in a multi-chip package over high density interconnects Jun 28, 2018 Issued
Array ( [id] => 16751530 [patent_doc_number] => 20210103539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => DELEGATION OF UNIVERSAL SERIAL BUS POWER AMONG MULTIPLE PORTS [patent_app_type] => utility [patent_app_number] => 17/048111 [patent_app_country] => US [patent_app_date] => 2018-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17048111 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/048111
DELEGATION OF UNIVERSAL SERIAL BUS POWER AMONG MULTIPLE PORTS Jun 13, 2018 Abandoned
Array ( [id] => 16032619 [patent_doc_number] => 10678730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Computing system framework and method for configuration thereof [patent_app_type] => utility [patent_app_number] => 15/990772 [patent_app_country] => US [patent_app_date] => 2018-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 8890 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15990772 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/990772
Computing system framework and method for configuration thereof May 27, 2018 Issued
Array ( [id] => 15187303 [patent_doc_number] => 20190364243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => METHOD AND DEVICE FOR DUAL CODECS TO TRANSFER DIGITAL CONTENT [patent_app_type] => utility [patent_app_number] => 15/988857 [patent_app_country] => US [patent_app_date] => 2018-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15988857 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/988857
METHOD AND DEVICE FOR DUAL CODECS TO TRANSFER DIGITAL CONTENT May 23, 2018 Abandoned
Array ( [id] => 13906153 [patent_doc_number] => 20190042281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => SYSTEM, METHOD, AND APPARATUS FOR DVSEC FOR EFFICIENT PERIPHERAL MANAGEMENT [patent_app_type] => utility [patent_app_number] => 15/987863 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987863 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987863
System, method, and apparatus for DVSEC for efficient peripheral management May 22, 2018 Issued
Array ( [id] => 15152041 [patent_doc_number] => 20190354498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => MEMORY ACCESS OPERATION SUSPEND/RESUME [patent_app_type] => utility [patent_app_number] => 15/982210 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5491 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982210 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/982210
Memory access operation suspend/resume May 16, 2018 Issued
Array ( [id] => 14856837 [patent_doc_number] => 10417146 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-17 [patent_title] => Real-time resource handling in resource retry queue [patent_app_type] => utility [patent_app_number] => 15/980713 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15980713 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/980713
Real-time resource handling in resource retry queue May 14, 2018 Issued
Array ( [id] => 17046845 [patent_doc_number] => 11100026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Reconfigurable server and server rack with same [patent_app_type] => utility [patent_app_number] => 16/610922 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 4959 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16610922 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/610922
Reconfigurable server and server rack with same May 14, 2018 Issued
Array ( [id] => 15093805 [patent_doc_number] => 20190341714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Information Handling System Mobile Adapter with Rotational Cable Management [patent_app_type] => utility [patent_app_number] => 15/971124 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15971124 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/971124
Information handling system mobile adapter with rotational cable management May 3, 2018 Issued
Array ( [id] => 15093799 [patent_doc_number] => 20190341711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => INFORMATION HANDLING SYSTEM MOBILE ADAPTER WITH VIDEO AND COMMUNICATIONS CIRCUIT BOARDS [patent_app_type] => utility [patent_app_number] => 15/971099 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15971099 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/971099
Information handling system mobile adapter with video and communications circuit boards May 3, 2018 Issued
Array ( [id] => 13906585 [patent_doc_number] => 20190042497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => HUB CIRCUIT FOR A DIMM HAVING MULTIPLE COMPONENTS THAT COMMUNICATE WITH A HOST [patent_app_type] => utility [patent_app_number] => 15/970639 [patent_app_country] => US [patent_app_date] => 2018-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15970639 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/970639
Hub circuit for a DIMM having multiple components that communicate with a host May 2, 2018 Issued
Array ( [id] => 15167663 [patent_doc_number] => 10489326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Device and system for aggregating networks and serving data from those networks to computers [patent_app_type] => utility [patent_app_number] => 15/969304 [patent_app_country] => US [patent_app_date] => 2018-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6683 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 401 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15969304 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/969304
Device and system for aggregating networks and serving data from those networks to computers May 1, 2018 Issued
Menu