Search

Fred M. Teskin

Examiner (ID: 1962, Phone: (571)272-1116 , Office: P/1762 )

Most Active Art Unit
1762
Art Unit(s)
1505, 1713, 1796, 2899, 1762
Total Applications
3798
Issued Applications
3195
Pending Applications
156
Abandoned Applications
473

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18826526 [patent_doc_number] => 11841802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Microprocessor that prevents same address load-load ordering violations [patent_app_type] => utility [patent_app_number] => 17/747815 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 68 [patent_no_of_words] => 58307 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747815 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747815
Microprocessor that prevents same address load-load ordering violations May 17, 2022 Issued
Array ( [id] => 19426644 [patent_doc_number] => 12086063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Physical address proxy reuse management [patent_app_type] => utility [patent_app_number] => 17/747556 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 68 [patent_no_of_words] => 58282 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747556
Physical address proxy reuse management May 17, 2022 Issued
Array ( [id] => 17992001 [patent_doc_number] => 20220358038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => MICROPROCESSOR THAT PREVENTS SAME ADDRESS LOAD-LOAD ORDERING VIOLATIONS USING PHYSICAL ADDRESS PROXIES [patent_app_type] => utility [patent_app_number] => 17/747784 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 58315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747784 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747784
Microprocessor that prevents same address load-load ordering violations using physical address proxies May 17, 2022 Issued
Array ( [id] => 18826526 [patent_doc_number] => 11841802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Microprocessor that prevents same address load-load ordering violations [patent_app_type] => utility [patent_app_number] => 17/747815 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 68 [patent_no_of_words] => 58307 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747815 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747815
Microprocessor that prevents same address load-load ordering violations May 17, 2022 Issued
Array ( [id] => 18872987 [patent_doc_number] => 11860794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Generational physical address proxies [patent_app_type] => utility [patent_app_number] => 17/747625 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 68 [patent_no_of_words] => 58234 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747625 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747625
Generational physical address proxies May 17, 2022 Issued
Array ( [id] => 18826526 [patent_doc_number] => 11841802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Microprocessor that prevents same address load-load ordering violations [patent_app_type] => utility [patent_app_number] => 17/747815 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 68 [patent_no_of_words] => 58307 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747815 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747815
Microprocessor that prevents same address load-load ordering violations May 17, 2022 Issued
Array ( [id] => 18787871 [patent_doc_number] => 20230376242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SYSTEM FOR COMPUTATIONAL STORAGE WITH HARDWARE-ASSISTANCE [patent_app_type] => utility [patent_app_number] => 17/746831 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746831 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746831
System for computational storage with hardware-assistance May 16, 2022 Issued
Array ( [id] => 19475549 [patent_doc_number] => 12105639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Methods for cache insertion and cache eviction in a cache system that includes a reverse cache and a main cache [patent_app_type] => utility [patent_app_number] => 17/663809 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9684 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663809 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663809
Methods for cache insertion and cache eviction in a cache system that includes a reverse cache and a main cache May 16, 2022 Issued
Array ( [id] => 18734749 [patent_doc_number] => 11803480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => System control using sparse data [patent_app_type] => utility [patent_app_number] => 17/662500 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13725 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662500 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/662500
System control using sparse data May 8, 2022 Issued
Array ( [id] => 18728011 [patent_doc_number] => 20230342304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => HIGH-THROUGHPUT REGULAR EXPRESSION PROCESSING WITH PATH PRIORITIES USING AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/660799 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17660799 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/660799
High-throughput regular expression processing with path priorities using an integrated circuit Apr 25, 2022 Issued
Array ( [id] => 18227242 [patent_doc_number] => 20230066236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => Criticality-Informed Caching Policies [patent_app_type] => utility [patent_app_number] => 17/727020 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17727020 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/727020
Criticality-informed caching policies Apr 21, 2022 Issued
Array ( [id] => 19443425 [patent_doc_number] => 12093697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Methods and apparatus to boot from block devices [patent_app_type] => utility [patent_app_number] => 17/721534 [patent_app_country] => US [patent_app_date] => 2022-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 19705 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721534 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721534
Methods and apparatus to boot from block devices Apr 14, 2022 Issued
Array ( [id] => 18499318 [patent_doc_number] => 20230222068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => SYSTEM AND METHOD FOR OPTIMIZING CACHED MEMORY COMPRISING VARYING DEGREES OF SLA AND CRG [patent_app_type] => utility [patent_app_number] => 17/715454 [patent_app_country] => US [patent_app_date] => 2022-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17715454 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/715454
SYSTEM AND METHOD FOR OPTIMIZING CACHED MEMORY COMPRISING VARYING DEGREES OF SLA AND CRG Apr 6, 2022 Abandoned
Array ( [id] => 18677990 [patent_doc_number] => 20230315637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => HOT LINE FAIRNESS MECHANISM FAVORING SOFTWARE FORWARD PROGRESS [patent_app_type] => utility [patent_app_number] => 17/713263 [patent_app_country] => US [patent_app_date] => 2022-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17713263 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/713263
Hot line fairness mechanism favoring software forward progress Apr 4, 2022 Issued
Array ( [id] => 18592032 [patent_doc_number] => 11740930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Global coherence operations [patent_app_type] => utility [patent_app_number] => 17/713287 [patent_app_country] => US [patent_app_date] => 2022-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 17676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17713287 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/713287
Global coherence operations Apr 4, 2022 Issued
Array ( [id] => 18677997 [patent_doc_number] => 20230315644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => CASTOUT HANDLING IN A DISTRIBUTED CACHE TOPOLOGY [patent_app_type] => utility [patent_app_number] => 17/708785 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708785 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/708785
Castout handling in a distributed cache topology Mar 29, 2022 Issued
Array ( [id] => 19182549 [patent_doc_number] => 11989137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Logging cache line lifetime hints when recording bit-accurate trace [patent_app_type] => utility [patent_app_number] => 18/548320 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 16671 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18548320 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/548320
Logging cache line lifetime hints when recording bit-accurate trace Mar 20, 2022 Issued
Array ( [id] => 18345689 [patent_doc_number] => 20230133799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS FOR PERFORMING PROGRAMMING OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/696638 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696638 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/696638
Semiconductor devices and methods for performing programming operations Mar 15, 2022 Issued
Array ( [id] => 18267780 [patent_doc_number] => 20230089022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MEMORY SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/689907 [patent_app_country] => US [patent_app_date] => 2022-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17689907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/689907
Memory system and method of writing data to storage areas constituting group Mar 7, 2022 Issued
Array ( [id] => 19514280 [patent_doc_number] => 20240345966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 18/293858 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18293858 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/293858
Information processing device and information processing method with lock for exclusive access to data in memory Mar 3, 2022 Issued
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