Search

Fred M. Teskin

Examiner (ID: 1962, Phone: (571)272-1116 , Office: P/1762 )

Most Active Art Unit
1762
Art Unit(s)
1505, 1713, 1796, 2899, 1762
Total Applications
3798
Issued Applications
3195
Pending Applications
156
Abandoned Applications
473

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19182541 [patent_doc_number] => 11989129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Multiple virtual NUMA domains within a single NUMA domain via operating system interface tables [patent_app_type] => utility [patent_app_number] => 16/986490 [patent_app_country] => US [patent_app_date] => 2020-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5631 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16986490 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/986490
Multiple virtual NUMA domains within a single NUMA domain via operating system interface tables Aug 5, 2020 Issued
Array ( [id] => 16423549 [patent_doc_number] => 20200348747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS [patent_app_type] => utility [patent_app_number] => 16/933407 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16933407 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/933407
Static power reduction in caches using deterministic naps Jul 19, 2020 Issued
Array ( [id] => 16423738 [patent_doc_number] => 20200348936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => METHOD OF MANAGING MULTI-TIER MEMORY DISPLACEMENT USING SOFTWARE CONTROLLED THRESHOLDS [patent_app_type] => utility [patent_app_number] => 16/927352 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927352 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927352
Method of managing multi-tier memory displacement using software controlled thresholds Jul 12, 2020 Issued
Array ( [id] => 17317134 [patent_doc_number] => 20210406183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => METHOD AND APPARATUS FOR A PAGE-LOCAL DELTA-BASED PREFETCHER [patent_app_type] => utility [patent_app_number] => 16/927786 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927786 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927786
Method and apparatus for a page-local delta-based prefetcher Jul 12, 2020 Issued
Array ( [id] => 17771235 [patent_doc_number] => 11403177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Data processing system for securing atomicity of transactions without generating separate commit command, and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/925656 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 19225 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925656 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/925656
Data processing system for securing atomicity of transactions without generating separate commit command, and operating method thereof Jul 9, 2020 Issued
Array ( [id] => 17771235 [patent_doc_number] => 11403177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Data processing system for securing atomicity of transactions without generating separate commit command, and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/925656 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 19225 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925656 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/925656
Data processing system for securing atomicity of transactions without generating separate commit command, and operating method thereof Jul 9, 2020 Issued
Array ( [id] => 17771235 [patent_doc_number] => 11403177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Data processing system for securing atomicity of transactions without generating separate commit command, and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/925656 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 19225 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925656 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/925656
Data processing system for securing atomicity of transactions without generating separate commit command, and operating method thereof Jul 9, 2020 Issued
Array ( [id] => 17771235 [patent_doc_number] => 11403177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Data processing system for securing atomicity of transactions without generating separate commit command, and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/925656 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 19225 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925656 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/925656
Data processing system for securing atomicity of transactions without generating separate commit command, and operating method thereof Jul 9, 2020 Issued
Array ( [id] => 16393196 [patent_doc_number] => 20200334137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => BIASED SAMPLING METHODOLOGY FOR WEAR LEVELING [patent_app_type] => utility [patent_app_number] => 16/921479 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921479 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/921479
Biased sampling methodology for wear leveling Jul 5, 2020 Issued
Array ( [id] => 17757390 [patent_doc_number] => 11397682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Memory-based synchronization of distributed operations [patent_app_type] => utility [patent_app_number] => 16/916153 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7755 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916153 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916153
Memory-based synchronization of distributed operations Jun 29, 2020 Issued
Array ( [id] => 18463175 [patent_doc_number] => 11687465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Spatial cache [patent_app_type] => utility [patent_app_number] => 16/910813 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 14680 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16910813 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/910813
Spatial cache Jun 23, 2020 Issued
Array ( [id] => 17589623 [patent_doc_number] => 11327896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => System control using sparse data [patent_app_type] => utility [patent_app_number] => 16/908182 [patent_app_country] => US [patent_app_date] => 2020-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16908182 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/908182
System control using sparse data Jun 21, 2020 Issued
Array ( [id] => 17294215 [patent_doc_number] => 20210390054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => CACHE MANAGEMENT CIRCUITS FOR PREDICTIVE ADJUSTMENT OF CACHE CONTROL POLICIES BASED ON PERSISTENT, HISTORY-BASED CACHE CONTROL INFORMATION [patent_app_type] => utility [patent_app_number] => 16/898872 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -39 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16898872 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/898872
Cache management circuits for predictive adjustment of cache control policies based on persistent, history-based cache control information Jun 10, 2020 Issued
Array ( [id] => 16315810 [patent_doc_number] => 20200294548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => METHOD FOR ACCESSING SHINGLED MAGNETIC RECORDING SMR DISK, AND SERVER [patent_app_type] => utility [patent_app_number] => 16/890642 [patent_app_country] => US [patent_app_date] => 2020-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16890642 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/890642
Method for accessing shingled magnetic recording SMR disk, and server Jun 1, 2020 Issued
Array ( [id] => 17771290 [patent_doc_number] => 11403232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Sequence thrashing avoidance via fall through estimation [patent_app_type] => utility [patent_app_number] => 16/888258 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16888258 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/888258
Sequence thrashing avoidance via fall through estimation May 28, 2020 Issued
Array ( [id] => 17515557 [patent_doc_number] => 11294707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Global coherence operations [patent_app_type] => utility [patent_app_number] => 16/882365 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 17666 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882365 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882365
Global coherence operations May 21, 2020 Issued
Array ( [id] => 16470391 [patent_doc_number] => 20200371928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS [patent_app_type] => utility [patent_app_number] => 16/882390 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882390 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882390
Write merging on stores with different privilege levels May 21, 2020 Issued
Array ( [id] => 16470387 [patent_doc_number] => 20200371924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => CONTROLLER WITH CACHING AND NON-CACHING MODES [patent_app_type] => utility [patent_app_number] => 16/882329 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882329 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882329
Controller with caching and non-caching modes May 21, 2020 Issued
Array ( [id] => 16675773 [patent_doc_number] => 20210064539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => UNIFIED ADDRESS TRANSLATION [patent_app_type] => utility [patent_app_number] => 16/874997 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874997 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874997
Unified address translation May 14, 2020 Issued
Array ( [id] => 16543456 [patent_doc_number] => 20200409871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => INFORMATION HANDLING APPARATUS AND METHOD FOR UNLOCKING A PERSISTENT REGION IN MEMORY [patent_app_type] => utility [patent_app_number] => 16/869102 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16869102 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/869102
Information handling apparatus and method for unlocking a persistent region in memory May 6, 2020 Issued
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