
Fred M. Teskin
Examiner (ID: 1962, Phone: (571)272-1116 , Office: P/1762 )
| Most Active Art Unit | 1762 |
| Art Unit(s) | 1505, 1713, 1796, 2899, 1762 |
| Total Applications | 3798 |
| Issued Applications | 3195 |
| Pending Applications | 156 |
| Abandoned Applications | 473 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20234405
[patent_doc_number] => 20250291724
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-18
[patent_title] => COMMUNICATION SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/982791
[patent_app_country] => US
[patent_app_date] => 2024-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23027
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 289
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18982791
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/982791 | COMMUNICATION SYSTEM | Dec 15, 2024 | Pending |
Array
(
[id] => 20828093
[patent_doc_number] => 12681660
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-07-14
[patent_title] => Memory architecture for block migration in ZNS
[patent_app_type] => utility
[patent_app_number] => 18/980680
[patent_app_country] => US
[patent_app_date] => 2024-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5072
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18980680
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/980680 | MEMORY ARCHITECTURE FOR BLOCK MIGRATION IN ZNS | Dec 12, 2024 | Issued |
Array
(
[id] => 20513060
[patent_doc_number] => 20260037161
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-02-05
[patent_title] => ADJUSTING POWER CONSUMPTION OF ONGOING OPERATIONS ON A SOLID STATE DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/977463
[patent_app_country] => US
[patent_app_date] => 2024-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1156
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18977463
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/977463 | ADJUSTING POWER CONSUMPTION OF ONGOING OPERATIONS ON A SOLID STATE DEVICE | Dec 10, 2024 | Pending |
Array
(
[id] => 20764558
[patent_doc_number] => 20260161542
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-06-11
[patent_title] => MECHANISM TO PROTECT A PROCESSOR'S SECURITY MODEL WHILE ALLOWING TRADITIONAL UNSAFE PRACTICES WITHIN A BOUNDED MEMORY RANGE
[patent_app_type] => utility
[patent_app_number] => 18/970594
[patent_app_country] => US
[patent_app_date] => 2024-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4202
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18970594
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/970594 | MECHANISM TO PROTECT A PROCESSOR'S SECURITY MODEL WHILE ALLOWING TRADITIONAL UNSAFE PRACTICES WITHIN A BOUNDED MEMORY RANGE | Dec 4, 2024 | Pending |
Array
(
[id] => 20249642
[patent_doc_number] => 20250298511
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => MEMORY STATUS BASED TRAFFIC ROUTING ON HETEROGENEOUS MEMORY SUBSYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/956020
[patent_app_country] => US
[patent_app_date] => 2024-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5249
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18956020
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/956020 | MEMORY STATUS BASED TRAFFIC ROUTING ON HETEROGENEOUS MEMORY SUBSYSTEM | Nov 21, 2024 | Pending |
Array
(
[id] => 20061468
[patent_doc_number] => 20250199690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-19
[patent_title] => DETECTING BLOCK SWITCHING DURING BACKGROUND OPERATIONS TO IMPROVE SEQUENTIAL WRITE PERFORMANCE
[patent_app_type] => utility
[patent_app_number] => 18/954833
[patent_app_country] => US
[patent_app_date] => 2024-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4472
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18954833
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/954833 | DETECTING BLOCK SWITCHING DURING BACKGROUND OPERATIONS TO IMPROVE SEQUENTIAL WRITE PERFORMANCE | Nov 20, 2024 | Pending |
Array
(
[id] => 19818869
[patent_doc_number] => 20250077076
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => NON-DETERMINISTIC MEMORY PROTOCOL
[patent_app_type] => utility
[patent_app_number] => 18/954809
[patent_app_country] => US
[patent_app_date] => 2024-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7213
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18954809
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/954809 | NON-DETERMINISTIC MEMORY PROTOCOL | Nov 20, 2024 | Pending |
Array
(
[id] => 20026967
[patent_doc_number] => 20250165189
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-22
[patent_title] => BIT STRING ARBITER COMPONENTS
[patent_app_type] => utility
[patent_app_number] => 18/948878
[patent_app_country] => US
[patent_app_date] => 2024-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3858
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18948878
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/948878 | BIT STRING ARBITER COMPONENTS | Nov 14, 2024 | Pending |
Array
(
[id] => 19772085
[patent_doc_number] => 20250053511
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-13
[patent_title] => SYSTEM AND METHOD FOR SHARING A CACHE LINE BETWEEN NON-CONTIGUOUS MEMORY AREAS
[patent_app_type] => utility
[patent_app_number] => 18/928244
[patent_app_country] => US
[patent_app_date] => 2024-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13242
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18928244
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/928244 | System and method for sharing a cache line between non-contiguous memory areas | Oct 27, 2024 | Issued |
Array
(
[id] => 19725800
[patent_doc_number] => 20250028551
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-23
[patent_title] => GLOBAL COHERENCE OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 18/908970
[patent_app_country] => US
[patent_app_date] => 2024-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17707
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18908970
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/908970 | GLOBAL COHERENCE OPERATIONS | Oct 7, 2024 | Pending |
Array
(
[id] => 19694739
[patent_doc_number] => 20250013284
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-09
[patent_title] => STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS
[patent_app_type] => utility
[patent_app_number] => 18/894180
[patent_app_country] => US
[patent_app_date] => 2024-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4640
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18894180
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/894180 | Static power reduction in caches using deterministic naps | Sep 23, 2024 | Issued |
Array
(
[id] => 20617061
[patent_doc_number] => 20260087161
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-03-26
[patent_title] => GRANULE PROTECTION CHECKING
[patent_app_type] => utility
[patent_app_number] => 18/894651
[patent_app_country] => US
[patent_app_date] => 2024-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15978
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18894651
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/894651 | GRANULE PROTECTION CHECKING | Sep 23, 2024 | Pending |
Array
(
[id] => 20601830
[patent_doc_number] => 20260079840
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-03-19
[patent_title] => DIRTY TRACKING BIT COMPRESSION
[patent_app_type] => utility
[patent_app_number] => 18/890178
[patent_app_country] => US
[patent_app_date] => 2024-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1223
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18890178
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/890178 | DIRTY TRACKING BIT COMPRESSION | Sep 18, 2024 | Pending |
Array
(
[id] => 19695017
[patent_doc_number] => 20250013562
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-09
[patent_title] => SYNCHRONIZED REQUEST HANDLING AT A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/887886
[patent_app_country] => US
[patent_app_date] => 2024-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11755
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18887886
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/887886 | Synchronized request handling at a memory device | Sep 16, 2024 | Issued |
Array
(
[id] => 19818915
[patent_doc_number] => 20250077122
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => FILE SYSTEM IMPROVEMENTS FOR ZONED STORAGE DEVICE OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 18/829981
[patent_app_country] => US
[patent_app_date] => 2024-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10268
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18829981
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/829981 | File system improvements for zoned storage device operations | Sep 9, 2024 | Issued |
Array
(
[id] => 19834326
[patent_doc_number] => 20250086112
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-13
[patent_title] => MEMORY CONTROL SYSTEM AND MEMORY CONTROL METHOD FOR REDUCING MEMORY TRAFFIC
[patent_app_type] => utility
[patent_app_number] => 18/827870
[patent_app_country] => US
[patent_app_date] => 2024-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3296
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18827870
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/827870 | MEMORY CONTROL SYSTEM AND MEMORY CONTROL METHOD FOR REDUCING MEMORY TRAFFIC | Sep 8, 2024 | Pending |
Array
(
[id] => 20035053
[patent_doc_number] => 20250173275
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-29
[patent_title] => STORAGE CONTROLLER, STORAGE DEVICE, AND STORAGE SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/827162
[patent_app_country] => US
[patent_app_date] => 2024-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9261
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18827162
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/827162 | STORAGE CONTROLLER, STORAGE DEVICE, AND STORAGE SYSTEM | Sep 5, 2024 | Pending |
Array
(
[id] => 19645064
[patent_doc_number] => 20240419584
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => USAGE DRIVEN MEMORY MAPPING
[patent_app_type] => utility
[patent_app_number] => 18/814148
[patent_app_country] => US
[patent_app_date] => 2024-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9055
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18814148
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/814148 | Usage driven memory mapping | Aug 22, 2024 | Issued |
Array
(
[id] => 19633114
[patent_doc_number] => 20240411563
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => METHODS AND APPARATUS TO BOOT FROM BLOCK DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/809646
[patent_app_country] => US
[patent_app_date] => 2024-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19707
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18809646
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/809646 | Methods and apparatus to boot from block devices | Aug 19, 2024 | Issued |
Array
(
[id] => 20805196
[patent_doc_number] => 12670103
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-30
[patent_title] => Paging metadata into memory
[patent_app_type] => utility
[patent_app_number] => 18/787516
[patent_app_country] => US
[patent_app_date] => 2024-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4546
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18787516
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/787516 | Paging metadata into memory | Jul 28, 2024 | Issued |