Search

Fred M. Teskin

Examiner (ID: 1962, Phone: (571)272-1116 , Office: P/1762 )

Most Active Art Unit
1762
Art Unit(s)
1505, 1713, 1796, 2899, 1762
Total Applications
3798
Issued Applications
3195
Pending Applications
156
Abandoned Applications
473

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19695031 [patent_doc_number] => 20250013576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => System Control Using Sparse Data [patent_app_type] => utility [patent_app_number] => 18/777905 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18777905 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/777905
System control using sparse data Jul 18, 2024 Issued
Array ( [id] => 19819201 [patent_doc_number] => 20250077408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => STORAGE CONTROLLER, STORAGE DEVICE, AND HOST-STORAGE SYSTEM INCLUDING THE STORAGE CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/774153 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774153 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/774153
STORAGE CONTROLLER, STORAGE DEVICE, AND HOST-STORAGE SYSTEM INCLUDING THE STORAGE CONTROLLER Jul 15, 2024 Pending
Array ( [id] => 20537572 [patent_doc_number] => 12554649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Profile guided memory trimming [patent_app_type] => utility [patent_app_number] => 18/769631 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4851 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769631 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769631
Profile guided memory trimming Jul 10, 2024 Issued
Array ( [id] => 19695033 [patent_doc_number] => 20250013578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => MEMORY MANAGEMENT METHOD BASED ON VIRTUAL MEMORY AND APPARATUS USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/763105 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763105 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763105
MEMORY MANAGEMENT METHOD BASED ON VIRTUAL MEMORY AND APPARATUS USING THE SAME Jul 2, 2024 Pending
Array ( [id] => 20454779 [patent_doc_number] => 12517833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Electronic devices, including memory devices, and operating methods thereof [patent_app_type] => utility [patent_app_number] => 18/762201 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4687 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762201 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762201
Electronic devices, including memory devices, and operating methods thereof Jul 1, 2024 Issued
Array ( [id] => 19530131 [patent_doc_number] => 20240354033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => Data Storage Device and Method for Device-Initiated Hibernation [patent_app_type] => utility [patent_app_number] => 18/760409 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760409 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760409
Data storage device and method for device-initiated hibernation Jun 30, 2024 Issued
Array ( [id] => 20249868 [patent_doc_number] => 20250298737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => SAFE SHARED-MEMORY COMMUNICATION [patent_app_type] => utility [patent_app_number] => 18/742099 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7837 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742099 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742099
SAFE SHARED-MEMORY COMMUNICATION Jun 12, 2024 Issued
Array ( [id] => 20380564 [patent_doc_number] => 20250363057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => CACHING PAGES IN COMPUTE REPLICAS BASED ON AGGREGATE USAGE OF PAGES ACROSS THE COMPUTE REPLICAS [patent_app_type] => utility [patent_app_number] => 18/669922 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669922 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/669922
CACHING PAGES IN COMPUTE REPLICAS BASED ON AGGREGATE USAGE OF PAGES ACROSS THE COMPUTE REPLICAS May 20, 2024 Pending
Array ( [id] => 20758158 [patent_doc_number] => 12650929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Smart memory module, host system having smart memory module, and method of operating smart memory module [patent_app_type] => utility [patent_app_number] => 18/668455 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3413 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668455 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668455
Smart memory module, host system having smart memory module, and method of operating smart memory module May 19, 2024 Issued
Array ( [id] => 19588404 [patent_doc_number] => 20240385961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => VALID DATA IDENTIFICATION FOR GARBAGE COLLECTION [patent_app_type] => utility [patent_app_number] => 18/664142 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664142 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664142
Valid data identification for garbage collection May 13, 2024 Issued
Array ( [id] => 19645085 [patent_doc_number] => 20240419605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/646506 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646506 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646506
SEMICONDUCTOR DEVICE Apr 24, 2024 Pending
Array ( [id] => 19383167 [patent_doc_number] => 20240273037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => METHODS FOR CACHE INSERTION AND CACHE EVICTION IN A CACHE SYSTEM THAT INCLUDES A REVERSE CACHE AND A MAIN CACHE [patent_app_type] => utility [patent_app_number] => 18/644246 [patent_app_country] => US [patent_app_date] => 2024-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9709 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18644246 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/644246
Methods for cache insertion and cache eviction in a cache system that includes a reverse cache and a main cache Apr 23, 2024 Issued
Array ( [id] => 19362917 [patent_doc_number] => 20240264951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => LOGGING CACHE LINE LIFETIME HINTS WHEN RECORDING BIT-ACCURATE TRACE [patent_app_type] => utility [patent_app_number] => 18/638454 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16695 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18638454 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/638454
Logging cache line lifetime hints when recording bit-accurate trace Apr 16, 2024 Issued
Array ( [id] => 20290137 [patent_doc_number] => 20250315380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => METHOD OF DETERMINING A CACHE SIZE USING AN ESTIMATION OF A NUMBER OF REQUESTS FOR CACHE MEMORY AND A SIZE OF THE REQUESTS [patent_app_type] => utility [patent_app_number] => 18/628916 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18628916 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/628916
Method of determining a cache size using an estimation of a number of requests for cache memory and a size of the requests Apr 7, 2024 Issued
Array ( [id] => 20234411 [patent_doc_number] => 20250291730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => Hardware assisted Page Migration in a Multi-Dielet Processing System [patent_app_type] => utility [patent_app_number] => 18/607525 [patent_app_country] => US [patent_app_date] => 2024-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607525 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607525
Hardware assisted page migration in a multi-dielet processing system Mar 16, 2024 Issued
Array ( [id] => 20234414 [patent_doc_number] => 20250291733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => MULTI-CORE PROCESSORS EVICTING CACHE LINES FROM LOWER-LEVEL CACHES TO HIGHER-LEVEL CACHES BY CORE-TO-CORE TRANSFERS [patent_app_type] => utility [patent_app_number] => 18/603147 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603147 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/603147
MULTI-CORE PROCESSORS EVICTING CACHE LINES FROM LOWER-LEVEL CACHES TO HIGHER-LEVEL CACHES BY CORE-TO-CORE TRANSFERS Mar 11, 2024 Pending
Array ( [id] => 19267436 [patent_doc_number] => 20240211139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY BUFFER MANAGEMENT ON HARDWARE DEVICES UTILIZING DISTRIBUTED DECENTRALIZED MEMORY BUFFER MONITORING [patent_app_type] => utility [patent_app_number] => 18/600150 [patent_app_country] => US [patent_app_date] => 2024-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18600150 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/600150
Memory buffer management on hardware devices utilizing distributed decentralized memory buffer monitoring Mar 7, 2024 Issued
Array ( [id] => 20388217 [patent_doc_number] => 12487943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Systems and methods for birth time-based FIFO cache reaping [patent_app_type] => utility [patent_app_number] => 18/598134 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598134 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/598134
Systems and methods for birth time-based FIFO cache reaping Mar 6, 2024 Issued
Array ( [id] => 20374146 [patent_doc_number] => 12481581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Apparatus and method thereof for dram initialization [patent_app_type] => utility [patent_app_number] => 18/594408 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594408 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594408
Apparatus and method thereof for dram initialization Mar 3, 2024 Issued
Array ( [id] => 20359035 [patent_doc_number] => 12475031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Very large address space using extended page tables [patent_app_type] => utility [patent_app_number] => 18/593435 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593435 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/593435
Very large address space using extended page tables Feb 29, 2024 Issued
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