Search

Fred Tzeng

Examiner (ID: 5378)

Most Active Art Unit
2627
Art Unit(s)
2186, 2686, 2627, 2752, 2651, 2695, 2625
Total Applications
1789
Issued Applications
1607
Pending Applications
63
Abandoned Applications
139

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1223288 [patent_doc_number] => 06704156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Self-writing of servo patterns in a disk drive using a printed reference pattern' [patent_app_type] => B1 [patent_app_number] => 09/494826 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 12507 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704156.pdf [firstpage_image] =>[orig_patent_app_number] => 09494826 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/494826
Self-writing of servo patterns in a disk drive using a printed reference pattern Jan 30, 2000 Issued
Array ( [id] => 1444106 [patent_doc_number] => 06496915 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Apparatus and method for reducing power consumption in an electronic data storage system' [patent_app_type] => B1 [patent_app_number] => 09/476590 [patent_app_country] => US [patent_app_date] => 1999-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496915.pdf [firstpage_image] =>[orig_patent_app_number] => 09476590 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476590
Apparatus and method for reducing power consumption in an electronic data storage system Dec 30, 1999 Issued
Array ( [id] => 7638624 [patent_doc_number] => 06397297 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Dual cache with multiple interconnection operation modes' [patent_app_type] => B1 [patent_app_number] => 09/474782 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2971 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397297.pdf [firstpage_image] =>[orig_patent_app_number] => 09474782 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474782
Dual cache with multiple interconnection operation modes Dec 29, 1999 Issued
Array ( [id] => 1552812 [patent_doc_number] => 06446156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Proposal of capacity tuning in the production process of storage disc drives' [patent_app_type] => B1 [patent_app_number] => 09/475530 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4710 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446156.pdf [firstpage_image] =>[orig_patent_app_number] => 09475530 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475530
Proposal of capacity tuning in the production process of storage disc drives Dec 29, 1999 Issued
Array ( [id] => 1406615 [patent_doc_number] => 06560675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method for controlling concurrent cache replace and return across an asynchronous interface' [patent_app_type] => B1 [patent_app_number] => 09/476293 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4592 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560675.pdf [firstpage_image] =>[orig_patent_app_number] => 09476293 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476293
Method for controlling concurrent cache replace and return across an asynchronous interface Dec 29, 1999 Issued
Array ( [id] => 1539180 [patent_doc_number] => 06412050 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Memory record update filtering' [patent_app_type] => B1 [patent_app_number] => 09/475984 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4020 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412050.pdf [firstpage_image] =>[orig_patent_app_number] => 09475984 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475984
Memory record update filtering Dec 29, 1999 Issued
Array ( [id] => 1431872 [patent_doc_number] => 06516384 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Method and apparatus to perform a round robin and locking cache replacement scheme' [patent_app_type] => B1 [patent_app_number] => 09/476444 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2640 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516384.pdf [firstpage_image] =>[orig_patent_app_number] => 09476444 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476444
Method and apparatus to perform a round robin and locking cache replacement scheme Dec 29, 1999 Issued
Array ( [id] => 1418737 [patent_doc_number] => 06546462 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'CLFLUSH micro-architectural implementation method and system' [patent_app_type] => B1 [patent_app_number] => 09/475759 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3982 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546462.pdf [firstpage_image] =>[orig_patent_app_number] => 09475759 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475759
CLFLUSH micro-architectural implementation method and system Dec 29, 1999 Issued
Array ( [id] => 1248874 [patent_doc_number] => 06678810 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'MFENCE and LFENCE micro-architectural implementation method and system' [patent_app_type] => B1 [patent_app_number] => 09/475363 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5151 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678810.pdf [firstpage_image] =>[orig_patent_app_number] => 09475363 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475363
MFENCE and LFENCE micro-architectural implementation method and system Dec 29, 1999 Issued
Array ( [id] => 1567455 [patent_doc_number] => 06438673 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Correlated address prediction' [patent_app_type] => B1 [patent_app_number] => 09/475063 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6619 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438673.pdf [firstpage_image] =>[orig_patent_app_number] => 09475063 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475063
Correlated address prediction Dec 29, 1999 Issued
Array ( [id] => 1584839 [patent_doc_number] => 06449702 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Memory bandwidth utilization through multiple priority request policy for isochronous data streams' [patent_app_type] => B1 [patent_app_number] => 09/475732 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2584 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449702.pdf [firstpage_image] =>[orig_patent_app_number] => 09475732 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475732
Memory bandwidth utilization through multiple priority request policy for isochronous data streams Dec 29, 1999 Issued
Array ( [id] => 1311405 [patent_doc_number] => 06625715 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'System and method for translation buffer accommodating multiple page sizes' [patent_app_type] => B1 [patent_app_number] => 09/475607 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 10493 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625715.pdf [firstpage_image] =>[orig_patent_app_number] => 09475607 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475607
System and method for translation buffer accommodating multiple page sizes Dec 29, 1999 Issued
Array ( [id] => 1519665 [patent_doc_number] => 06421769 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Efficient memory management for channel drivers in next generation I/O system' [patent_app_type] => B1 [patent_app_number] => 09/475610 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2700 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421769.pdf [firstpage_image] =>[orig_patent_app_number] => 09475610 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475610
Efficient memory management for channel drivers in next generation I/O system Dec 29, 1999 Issued
Array ( [id] => 1552938 [patent_doc_number] => 06446182 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method for a memory organization by physical zones in a computerized or data processing machine or arrangement and the computerized or data processing machine or arrangement for using the method' [patent_app_type] => B1 [patent_app_number] => 09/470953 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7830 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446182.pdf [firstpage_image] =>[orig_patent_app_number] => 09470953 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470953
Method for a memory organization by physical zones in a computerized or data processing machine or arrangement and the computerized or data processing machine or arrangement for using the method Dec 22, 1999 Issued
Array ( [id] => 1524906 [patent_doc_number] => 06415368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'System and method for caching' [patent_app_type] => B1 [patent_app_number] => 09/470126 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4678 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415368.pdf [firstpage_image] =>[orig_patent_app_number] => 09470126 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470126
System and method for caching Dec 21, 1999 Issued
Array ( [id] => 1584859 [patent_doc_number] => 06449706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Method and apparatus for accessing unaligned data' [patent_app_type] => B1 [patent_app_number] => 09/470015 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2121 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449706.pdf [firstpage_image] =>[orig_patent_app_number] => 09470015 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470015
Method and apparatus for accessing unaligned data Dec 21, 1999 Issued
Array ( [id] => 1431432 [patent_doc_number] => 06519685 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Cache states for multiprocessor cache coherency protocols' [patent_app_type] => B1 [patent_app_number] => 09/470274 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6721 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519685.pdf [firstpage_image] =>[orig_patent_app_number] => 09470274 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470274
Cache states for multiprocessor cache coherency protocols Dec 21, 1999 Issued
Array ( [id] => 1308875 [patent_doc_number] => 06629217 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Method and apparatus for improving read latency for processor to system memory read transactions' [patent_app_type] => B1 [patent_app_number] => 09/469653 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2521 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629217.pdf [firstpage_image] =>[orig_patent_app_number] => 09469653 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/469653
Method and apparatus for improving read latency for processor to system memory read transactions Dec 21, 1999 Issued
Array ( [id] => 1423456 [patent_doc_number] => 06539453 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Storage system including means for management of a memory with anti-attrition, and process of anti-attrition management of a memory' [patent_app_type] => B1 [patent_app_number] => 09/468879 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3128 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539453.pdf [firstpage_image] =>[orig_patent_app_number] => 09468879 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468879
Storage system including means for management of a memory with anti-attrition, and process of anti-attrition management of a memory Dec 21, 1999 Issued
Array ( [id] => 1567320 [patent_doc_number] => 06438648 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'System apparatus and method for managing multiple host computer operating requirements in a data storage system' [patent_app_type] => B1 [patent_app_number] => 09/470257 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5987 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438648.pdf [firstpage_image] =>[orig_patent_app_number] => 09470257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470257
System apparatus and method for managing multiple host computer operating requirements in a data storage system Dec 21, 1999 Issued
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