Search

Fred Tzeng

Examiner (ID: 5378)

Most Active Art Unit
2627
Art Unit(s)
2186, 2686, 2627, 2752, 2651, 2695, 2625
Total Applications
1789
Issued Applications
1607
Pending Applications
63
Abandoned Applications
139

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1431206 [patent_doc_number] => 06523098 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Mechanism for efficient low priority write draining' [patent_app_type] => B1 [patent_app_number] => 09/469676 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2889 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523098.pdf [firstpage_image] =>[orig_patent_app_number] => 09469676 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/469676
Mechanism for efficient low priority write draining Dec 21, 1999 Issued
Array ( [id] => 1431899 [patent_doc_number] => 06516396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Means to extend tTR range of RDRAMS via the RDRAM memory controller' [patent_app_type] => B1 [patent_app_number] => 09/470300 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5450 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516396.pdf [firstpage_image] =>[orig_patent_app_number] => 09470300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470300
Means to extend tTR range of RDRAMS via the RDRAM memory controller Dec 21, 1999 Issued
Array ( [id] => 7644140 [patent_doc_number] => 06473834 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Method and apparatus for prevent stalling of cache reads during return of multiple data words' [patent_app_type] => B1 [patent_app_number] => 09/469903 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2512 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473834.pdf [firstpage_image] =>[orig_patent_app_number] => 09469903 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/469903
Method and apparatus for prevent stalling of cache reads during return of multiple data words Dec 21, 1999 Issued
Array ( [id] => 1421059 [patent_doc_number] => 06542960 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'System and method for parity caching based on stripe locking in raid data storage' [patent_app_type] => B1 [patent_app_number] => 09/464127 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3466 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542960.pdf [firstpage_image] =>[orig_patent_app_number] => 09464127 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/464127
System and method for parity caching based on stripe locking in raid data storage Dec 15, 1999 Issued
Array ( [id] => 1567393 [patent_doc_number] => 06438662 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Information processing device capable of allowing the maximum processing performance of microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/459931 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2857 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438662.pdf [firstpage_image] =>[orig_patent_app_number] => 09459931 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/459931
Information processing device capable of allowing the maximum processing performance of microprocessor Dec 13, 1999 Issued
Array ( [id] => 1456784 [patent_doc_number] => 06457111 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and system for allocation of a persistence indicator for an object in an object-oriented environment' [patent_app_type] => B1 [patent_app_number] => 09/460774 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5687 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457111.pdf [firstpage_image] =>[orig_patent_app_number] => 09460774 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460774
Method and system for allocation of a persistence indicator for an object in an object-oriented environment Dec 13, 1999 Issued
Array ( [id] => 1584731 [patent_doc_number] => 06449683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Using non-volatile memory for power management in a computer' [patent_app_type] => B1 [patent_app_number] => 09/461644 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1905 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449683.pdf [firstpage_image] =>[orig_patent_app_number] => 09461644 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461644
Using non-volatile memory for power management in a computer Dec 13, 1999 Issued
Array ( [id] => 1601994 [patent_doc_number] => 06385697 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'System and method for cache process' [patent_app_type] => B1 [patent_app_number] => 09/461092 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 16331 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 622 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385697.pdf [firstpage_image] =>[orig_patent_app_number] => 09461092 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461092
System and method for cache process Dec 13, 1999 Issued
Array ( [id] => 1357029 [patent_doc_number] => 06591342 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Memory disambiguation for large instruction windows' [patent_app_type] => B1 [patent_app_number] => 09/461410 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8513 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591342.pdf [firstpage_image] =>[orig_patent_app_number] => 09461410 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461410
Memory disambiguation for large instruction windows Dec 13, 1999 Issued
Array ( [id] => 1485009 [patent_doc_number] => 06453397 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Single chip microcomputer internally including a flash memory' [patent_app_type] => B1 [patent_app_number] => 09/460623 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2659 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453397.pdf [firstpage_image] =>[orig_patent_app_number] => 09460623 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460623
Single chip microcomputer internally including a flash memory Dec 13, 1999 Issued
Array ( [id] => 1411533 [patent_doc_number] => 06553458 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Integrated redundant storage device' [patent_app_type] => B1 [patent_app_number] => 09/460581 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3057 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553458.pdf [firstpage_image] =>[orig_patent_app_number] => 09460581 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460581
Integrated redundant storage device Dec 13, 1999 Issued
Array ( [id] => 1444089 [patent_doc_number] => 06496907 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'System and method for updating from a read-only to a read-write entry and concurrently invalidating stale cache copies from head-to-tail and tail-to-head directions' [patent_app_type] => B1 [patent_app_number] => 09/426058 [patent_app_country] => US [patent_app_date] => 1999-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5897 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496907.pdf [firstpage_image] =>[orig_patent_app_number] => 09426058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/426058
System and method for updating from a read-only to a read-write entry and concurrently invalidating stale cache copies from head-to-tail and tail-to-head directions Oct 21, 1999 Issued
Array ( [id] => 1097366 [patent_doc_number] => 06826668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'System and method for reorganizing data on a disk drive to improve spatial locality' [patent_app_type] => B1 [patent_app_number] => 09/412902 [patent_app_country] => US [patent_app_date] => 1999-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3637 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826668.pdf [firstpage_image] =>[orig_patent_app_number] => 09412902 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/412902
System and method for reorganizing data on a disk drive to improve spatial locality Oct 4, 1999 Issued
Array ( [id] => 1587440 [patent_doc_number] => 06425063 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Method and arrangement for memory management' [patent_app_type] => B1 [patent_app_number] => 09/412635 [patent_app_country] => US [patent_app_date] => 1999-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 4894 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425063.pdf [firstpage_image] =>[orig_patent_app_number] => 09412635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/412635
Method and arrangement for memory management Oct 4, 1999 Issued
Array ( [id] => 1444075 [patent_doc_number] => 06496901 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Mapping variable size data blocks into a fixed block structure' [patent_app_type] => B1 [patent_app_number] => 09/401644 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4981 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496901.pdf [firstpage_image] =>[orig_patent_app_number] => 09401644 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401644
Mapping variable size data blocks into a fixed block structure Sep 21, 1999 Issued
Array ( [id] => 4280678 [patent_doc_number] => 06260106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Synchronous data storage system having re-drive circuits for reduced signal line loading' [patent_app_type] => 1 [patent_app_number] => 9/401444 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5329 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260106.pdf [firstpage_image] =>[orig_patent_app_number] => 401444 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401444
Synchronous data storage system having re-drive circuits for reduced signal line loading Sep 21, 1999 Issued
Array ( [id] => 1572366 [patent_doc_number] => 06378044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method and system for cache replacement among configurable cache sets' [patent_app_type] => B1 [patent_app_number] => 09/401046 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4813 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 384 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378044.pdf [firstpage_image] =>[orig_patent_app_number] => 09401046 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401046
Method and system for cache replacement among configurable cache sets Sep 21, 1999 Issued
Array ( [id] => 1357112 [patent_doc_number] => 06591348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Method and system for resolution of transaction collisions to achieve global coherence in a distributed symmetric multiprocessor system' [patent_app_type] => B1 [patent_app_number] => 09/392833 [patent_app_country] => US [patent_app_date] => 1999-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 14638 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591348.pdf [firstpage_image] =>[orig_patent_app_number] => 09392833 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392833
Method and system for resolution of transaction collisions to achieve global coherence in a distributed symmetric multiprocessor system Sep 8, 1999 Issued
Array ( [id] => 1584853 [patent_doc_number] => 06449705 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Method and apparatus for improving performance of drive linking through use of hash tables' [patent_app_type] => B1 [patent_app_number] => 09/392832 [patent_app_country] => US [patent_app_date] => 1999-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4238 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449705.pdf [firstpage_image] =>[orig_patent_app_number] => 09392832 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392832
Method and apparatus for improving performance of drive linking through use of hash tables Sep 8, 1999 Issued
Array ( [id] => 1557519 [patent_doc_number] => 06401170 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'RAID systems during non-fault and faulty conditions on a fiber channel arbitrated loop, SCSI bus or switch fabric configuration' [patent_app_type] => B1 [patent_app_number] => 09/376324 [patent_app_country] => US [patent_app_date] => 1999-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5425 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401170.pdf [firstpage_image] =>[orig_patent_app_number] => 09376324 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376324
RAID systems during non-fault and faulty conditions on a fiber channel arbitrated loop, SCSI bus or switch fabric configuration Aug 17, 1999 Issued
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