Search

Fred Tzeng

Examiner (ID: 5378)

Most Active Art Unit
2627
Art Unit(s)
2186, 2686, 2627, 2752, 2651, 2695, 2625
Total Applications
1789
Issued Applications
1607
Pending Applications
63
Abandoned Applications
139

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1401237 [patent_doc_number] => 06564307 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Method, system, and program for logically erasing data' [patent_app_type] => B1 [patent_app_number] => 09/376872 [patent_app_country] => US [patent_app_date] => 1999-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5888 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564307.pdf [firstpage_image] =>[orig_patent_app_number] => 09376872 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376872
Method, system, and program for logically erasing data Aug 17, 1999 Issued
Array ( [id] => 4349496 [patent_doc_number] => 06321292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'External storage control device and data transfer method between external storage control devices' [patent_app_type] => 1 [patent_app_number] => 9/375357 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2893 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321292.pdf [firstpage_image] =>[orig_patent_app_number] => 375357 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/375357
External storage control device and data transfer method between external storage control devices Aug 16, 1999 Issued
Array ( [id] => 1521718 [patent_doc_number] => 06502171 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data' [patent_app_type] => B1 [patent_app_number] => 09/368231 [patent_app_country] => US [patent_app_date] => 1999-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7015 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502171.pdf [firstpage_image] =>[orig_patent_app_number] => 09368231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368231
Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data Aug 3, 1999 Issued
Array ( [id] => 1429206 [patent_doc_number] => 06529992 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Self-contained application disk for automatically launching application software or starting devices and peripherals' [patent_app_type] => B1 [patent_app_number] => 09/360337 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5340 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529992.pdf [firstpage_image] =>[orig_patent_app_number] => 09360337 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360337
Self-contained application disk for automatically launching application software or starting devices and peripherals Jul 25, 1999 Issued
Array ( [id] => 943528 [patent_doc_number] => 06970976 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-29 [patent_title] => 'Layered local cache with lower level cache optimizing allocation mechanism' [patent_app_type] => utility [patent_app_number] => 09/340074 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7725 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/970/06970976.pdf [firstpage_image] =>[orig_patent_app_number] => 09340074 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340074
Layered local cache with lower level cache optimizing allocation mechanism Jun 24, 1999 Issued
Array ( [id] => 5830458 [patent_doc_number] => 20020069325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'CACHING METHOD USING CACHE DATA STORED IN DYNAMIC RAM EMBEDDED IN LOGIC CHIP AND CACHE TAG STORED IN STATIC RAM EXTERNAL TO LOGIC CHIP' [patent_app_type] => new [patent_app_number] => 09/344660 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2233 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20020069325.pdf [firstpage_image] =>[orig_patent_app_number] => 09344660 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344660
Caching method using cache data stored in dynamic RAM embedded in logic chip and cache tag stored in static RAM external to logic chip Jun 24, 1999 Issued
Array ( [id] => 1501542 [patent_doc_number] => 06405285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Layered local cache mechanism with split register load bus and cache load bus' [patent_app_type] => B1 [patent_app_number] => 09/340076 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7821 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405285.pdf [firstpage_image] =>[orig_patent_app_number] => 09340076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340076
Layered local cache mechanism with split register load bus and cache load bus Jun 24, 1999 Issued
Array ( [id] => 1279493 [patent_doc_number] => 06654854 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Caching method using cache tag and cache data stored in dynamic RAM embedded in logic chip' [patent_app_type] => B1 [patent_app_number] => 09/344460 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2314 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654854.pdf [firstpage_image] =>[orig_patent_app_number] => 09344460 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344460
Caching method using cache tag and cache data stored in dynamic RAM embedded in logic chip Jun 24, 1999 Issued
Array ( [id] => 1595928 [patent_doc_number] => 06484247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'System and method for storing and retrieving objects' [patent_app_type] => B1 [patent_app_number] => 09/340337 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11979 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484247.pdf [firstpage_image] =>[orig_patent_app_number] => 09340337 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340337
System and method for storing and retrieving objects Jun 24, 1999 Issued
Array ( [id] => 7638621 [patent_doc_number] => 06397300 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'High performance store instruction management via imprecise local cache update mechanism' [patent_app_type] => B1 [patent_app_number] => 09/340078 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7972 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397300.pdf [firstpage_image] =>[orig_patent_app_number] => 09340078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340078
High performance store instruction management via imprecise local cache update mechanism Jun 24, 1999 Issued
Array ( [id] => 1552861 [patent_doc_number] => 06446166 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method for upper level cache victim selection management by a lower level cache' [patent_app_type] => B1 [patent_app_number] => 09/340073 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7850 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446166.pdf [firstpage_image] =>[orig_patent_app_number] => 09340073 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340073
Method for upper level cache victim selection management by a lower level cache Jun 24, 1999 Issued
Array ( [id] => 1601992 [patent_doc_number] => 06385696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Embedded cache with way size bigger than page size' [patent_app_type] => B1 [patent_app_number] => 09/344757 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2811 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385696.pdf [firstpage_image] =>[orig_patent_app_number] => 09344757 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344757
Embedded cache with way size bigger than page size Jun 24, 1999 Issued
Array ( [id] => 7642381 [patent_doc_number] => 06430665 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'System and method for heuristically allocating memory' [patent_app_type] => B1 [patent_app_number] => 09/339808 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2566 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430665.pdf [firstpage_image] =>[orig_patent_app_number] => 09339808 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/339808
System and method for heuristically allocating memory Jun 24, 1999 Issued
Array ( [id] => 1495322 [patent_doc_number] => 06418513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Queue-less and state-less layered local data cache mechanism' [patent_app_type] => B1 [patent_app_number] => 09/340077 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7668 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418513.pdf [firstpage_image] =>[orig_patent_app_number] => 09340077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340077
Queue-less and state-less layered local data cache mechanism Jun 24, 1999 Issued
Array ( [id] => 1460011 [patent_doc_number] => 06463507 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Layered local cache with lower level cache updating upper and lower level cache directories' [patent_app_type] => B1 [patent_app_number] => 09/340082 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7701 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463507.pdf [firstpage_image] =>[orig_patent_app_number] => 09340082 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340082
Layered local cache with lower level cache updating upper and lower level cache directories Jun 24, 1999 Issued
Array ( [id] => 1587455 [patent_doc_number] => 06425067 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Systems and methods for implementing pointer management' [patent_app_type] => B1 [patent_app_number] => 09/340282 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2027 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425067.pdf [firstpage_image] =>[orig_patent_app_number] => 09340282 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340282
Systems and methods for implementing pointer management Jun 24, 1999 Issued
Array ( [id] => 1432385 [patent_doc_number] => 06505277 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Method for just-in-time delivery of load data by intervening caches' [patent_app_type] => B1 [patent_app_number] => 09/344057 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7641 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505277.pdf [firstpage_image] =>[orig_patent_app_number] => 09344057 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344057
Method for just-in-time delivery of load data by intervening caches Jun 24, 1999 Issued
Array ( [id] => 1484973 [patent_doc_number] => 06453389 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Optimizing computer performance by using data compression principles to minimize a loss function' [patent_app_type] => B1 [patent_app_number] => 09/340279 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 17908 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453389.pdf [firstpage_image] =>[orig_patent_app_number] => 09340279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340279
Optimizing computer performance by using data compression principles to minimize a loss function Jun 24, 1999 Issued
Array ( [id] => 1604481 [patent_doc_number] => 06434667 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Layered local cache with imprecise reload mechanism' [patent_app_type] => B1 [patent_app_number] => 09/340075 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7707 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434667.pdf [firstpage_image] =>[orig_patent_app_number] => 09340075 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340075
Layered local cache with imprecise reload mechanism Jun 24, 1999 Issued
Array ( [id] => 1549606 [patent_doc_number] => 06374338 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method for performing configuration tasks prior to and including memory configuration within a processor-based system' [patent_app_type] => B1 [patent_app_number] => 09/344051 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3168 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374338.pdf [firstpage_image] =>[orig_patent_app_number] => 09344051 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344051
Method for performing configuration tasks prior to and including memory configuration within a processor-based system Jun 24, 1999 Issued
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