Fred Tzeng

Array ( [id] => 1519663 [patent_doc_number] => 06421768 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Method and system for authentication and single sign on using cryptographically assured cookies in a distributed computer environment' [patent_app_type] => B1 [patent_app_number] => 09/305423 [patent_app_country] => US [patent_app_date] => 1999-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3757 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421768.pdf [firstpage_image] =>[orig_patent_app_number] => 09305423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1524914 [patent_doc_number] => 06415370 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/272103 [patent_app_country] => US [patent_app_date] => 1999-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 12259 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415370.pdf [firstpage_image] =>[orig_patent_app_number] => 09272103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 567686 [patent_doc_number] => 07161757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-09 [patent_title] => 'Method and apparatus for controlling a disk drive under a power loss condition' [patent_app_type] => utility [patent_app_number] => 09/914170 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3354 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/161/07161757.pdf [firstpage_image] =>[orig_patent_app_number] => 09914170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1549541 [patent_doc_number] => 06374325 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Content addressable memory (CAM)' [patent_app_type] => B1 [patent_app_number] => 09/251517 [patent_app_country] => US [patent_app_date] => 1999-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4103 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374325.pdf [firstpage_image] =>[orig_patent_app_number] => 09251517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1553802 [patent_doc_number] => 06347367 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures' [patent_app_type] => B1 [patent_app_number] => 09/240647 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5525 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347367.pdf [firstpage_image] =>[orig_patent_app_number] => 09240647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4323985 [patent_doc_number] => 06189082 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Burst access of registers at non-consecutive addresses using a mapping control word' [patent_app_type] => 1 [patent_app_number] => 9/240724 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189082.pdf [firstpage_image] =>[orig_patent_app_number] => 240724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1474979 [patent_doc_number] => 06408371 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Device to access memory based on a programmable page limit' [patent_app_type] => B1 [patent_app_number] => 09/240526 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408371.pdf [firstpage_image] =>[orig_patent_app_number] => 09240526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1460019 [patent_doc_number] => 06463509 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Preloading data in a cache memory according to user-specified preload criteria' [patent_app_type] => B1 [patent_app_number] => 09/238656 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10108 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463509.pdf [firstpage_image] =>[orig_patent_app_number] => 09238656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1456712 [patent_doc_number] => 06457094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-24 [patent_title] => 'Memory array architecture supporting block write operation' [patent_app_type] => B2 [patent_app_number] => 09/235222 [patent_app_country] => US [patent_app_date] => 1999-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5669 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457094.pdf [firstpage_image] =>[orig_patent_app_number] => 09235222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4426908 [patent_doc_number] => 06195732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Storage device capacity management' [patent_app_type] => 1 [patent_app_number] => 9/235613 [patent_app_country] => US [patent_app_date] => 1999-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5613 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195732.pdf [firstpage_image] =>[orig_patent_app_number] => 235613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374697 [patent_doc_number] => 06170043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Method for controlling an optic disk' [patent_app_type] => 1 [patent_app_number] => 9/234977 [patent_app_country] => US [patent_app_date] => 1999-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3571 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170043.pdf [firstpage_image] =>[orig_patent_app_number] => 234977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4280919 [patent_doc_number] => 06260122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Memory device' [patent_app_type] => 1 [patent_app_number] => 9/235842 [patent_app_country] => US [patent_app_date] => 1999-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1856 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260122.pdf [firstpage_image] =>[orig_patent_app_number] => 235842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4292206 [patent_doc_number] => 06247097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions' [patent_app_type] => 1 [patent_app_number] => 9/235474 [patent_app_country] => US [patent_app_date] => 1999-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 13357 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247097.pdf [firstpage_image] =>[orig_patent_app_number] => 235474 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4349659 [patent_doc_number] => 06321304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'System and method for deleting read-only head entries in multi-processor computer systems supporting cache coherence with mixed protocols' [patent_app_type] => 1 [patent_app_number] => 9/235588 [patent_app_country] => US [patent_app_date] => 1999-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4426 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321304.pdf [firstpage_image] =>[orig_patent_app_number] => 235588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4381268 [patent_doc_number] => 06256711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method for purging unused data from a cache memory' [patent_app_type] => 1 [patent_app_number] => 9/221378 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2900 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256711.pdf [firstpage_image] =>[orig_patent_app_number] => 221378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1604493 [patent_doc_number] => 06434679 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Architecture for vital data management in a multi-module machine and process for implementing an architecture of this type' [patent_app_type] => B1 [patent_app_number] => 09/199346 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434679.pdf [firstpage_image] =>[orig_patent_app_number] => 09199346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1580370 [patent_doc_number] => 06470434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Computer system and method for accessing a computer-readable medium' [patent_app_type] => B1 [patent_app_number] => 09/198701 [patent_app_country] => US [patent_app_date] => 1998-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 7500 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470434.pdf [firstpage_image] =>[orig_patent_app_number] => 09198701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7634998 [patent_doc_number] => 06381668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Address mapping for system memory' [patent_app_type] => B1 [patent_app_number] => 09/194275 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 4688 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381668.pdf [firstpage_image] =>[orig_patent_app_number] => 09194275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1361219 [patent_doc_number] => 06587918 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Method for controlling refresh of a multibank memory device' [patent_app_type] => B1 [patent_app_number] => 09/196569 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3508 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587918.pdf [firstpage_image] =>[orig_patent_app_number] => 09196569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424456 [patent_doc_number] => 06266733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Two-level mini-block storage system for volume data sets' [patent_app_type] => 1 [patent_app_number] => 9/191865 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9156 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266733.pdf [firstpage_image] =>[orig_patent_app_number] => 191865 [rel_patent_id] =>[rel_patent_doc_number] =>)