
Fred Tzeng
Examiner (ID: 5378)
| Most Active Art Unit | 2627 |
| Art Unit(s) | 2186, 2686, 2627, 2752, 2651, 2695, 2625 |
| Total Applications | 1789 |
| Issued Applications | 1607 |
| Pending Applications | 63 |
| Abandoned Applications | 139 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4238586
[patent_doc_number] => 06088741
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Storage medium system which uses a contactless memory card'
[patent_app_type] => 1
[patent_app_number] => 8/981785
[patent_app_country] => US
[patent_app_date] => 1998-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11655
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/088/06088741.pdf
[firstpage_image] =>[orig_patent_app_number] => 981785
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/981785 | Storage medium system which uses a contactless memory card | Mar 8, 1998 | Issued |
Array
(
[id] => 4260353
[patent_doc_number] => 06167496
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-26
[patent_title] => 'Data stream optimization system for video on demand'
[patent_app_type] => 1
[patent_app_number] => 9/025167
[patent_app_country] => US
[patent_app_date] => 1998-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3825
[patent_no_of_claims] => 10
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/167/06167496.pdf
[firstpage_image] =>[orig_patent_app_number] => 025167
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/025167 | Data stream optimization system for video on demand | Feb 17, 1998 | Issued |
Array
(
[id] => 4426903
[patent_doc_number] => 06195729
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'Deallocation with cache update protocol (L2 evictions)'
[patent_app_type] => 1
[patent_app_number] => 9/024317
[patent_app_country] => US
[patent_app_date] => 1998-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3375
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/195/06195729.pdf
[firstpage_image] =>[orig_patent_app_number] => 024317
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/024317 | Deallocation with cache update protocol (L2 evictions) | Feb 16, 1998 | Issued |
Array
(
[id] => 4269212
[patent_doc_number] => 06138218
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'Forward progress on retried snoop hits by altering the coherency state of a local cache'
[patent_app_type] => 1
[patent_app_number] => 9/024616
[patent_app_country] => US
[patent_app_date] => 1998-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 5019
[patent_no_of_claims] => 28
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/138/06138218.pdf
[firstpage_image] =>[orig_patent_app_number] => 024616
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/024616 | Forward progress on retried snoop hits by altering the coherency state of a local cache | Feb 16, 1998 | Issued |
Array
(
[id] => 4292220
[patent_doc_number] => 06247098
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-12
[patent_title] => 'Cache coherency protocol with selectively implemented tagged state'
[patent_app_type] => 1
[patent_app_number] => 9/024381
[patent_app_country] => US
[patent_app_date] => 1998-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 10478
[patent_no_of_claims] => 19
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[pdf_file] => patents/06/247/06247098.pdf
[firstpage_image] =>[orig_patent_app_number] => 024381
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/024381 | Cache coherency protocol with selectively implemented tagged state | Feb 16, 1998 | Issued |
Array
(
[id] => 4223826
[patent_doc_number] => 06078990
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-20
[patent_title] => 'Volume set configuration using a single operational view'
[patent_app_type] => 1
[patent_app_number] => 9/020163
[patent_app_country] => US
[patent_app_date] => 1998-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 20
[patent_no_of_words] => 27829
[patent_no_of_claims] => 21
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/078/06078990.pdf
[firstpage_image] =>[orig_patent_app_number] => 020163
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/020163 | Volume set configuration using a single operational view | Feb 5, 1998 | Issued |
Array
(
[id] => 1601968
[patent_doc_number] => 06385689
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-07
[patent_title] => 'Memory and a data processor including a memory'
[patent_app_type] => B1
[patent_app_number] => 09/020088
[patent_app_country] => US
[patent_app_date] => 1998-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 4142
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/385/06385689.pdf
[firstpage_image] =>[orig_patent_app_number] => 09020088
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/020088 | Memory and a data processor including a memory | Feb 5, 1998 | Issued |
Array
(
[id] => 4162439
[patent_doc_number] => 06032238
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'Overlapped DMA line transfers'
[patent_app_type] => 1
[patent_app_number] => 9/020123
[patent_app_country] => US
[patent_app_date] => 1998-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3634
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 195
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/032/06032238.pdf
[firstpage_image] =>[orig_patent_app_number] => 020123
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/020123 | Overlapped DMA line transfers | Feb 5, 1998 | Issued |
Array
(
[id] => 4351826
[patent_doc_number] => 06314493
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Branch history cache'
[patent_app_type] => 1
[patent_app_number] => 9/018688
[patent_app_country] => US
[patent_app_date] => 1998-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 10217
[patent_no_of_claims] => 33
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/314/06314493.pdf
[firstpage_image] =>[orig_patent_app_number] => 018688
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/018688 | Branch history cache | Feb 2, 1998 | Issued |
Array
(
[id] => 4192550
[patent_doc_number] => 06141734
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol'
[patent_app_type] => 1
[patent_app_number] => 9/017752
[patent_app_country] => US
[patent_app_date] => 1998-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5319
[patent_no_of_claims] => 15
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[pdf_file] => patents/06/141/06141734.pdf
[firstpage_image] =>[orig_patent_app_number] => 017752
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/017752 | Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol | Feb 2, 1998 | Issued |
Array
(
[id] => 4371245
[patent_doc_number] => 06216214
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-10
[patent_title] => 'Apparatus and method for a virtual hashed page table'
[patent_app_type] => 1
[patent_app_number] => 9/018326
[patent_app_country] => US
[patent_app_date] => 1998-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/216/06216214.pdf
[firstpage_image] =>[orig_patent_app_number] => 018326
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/018326 | Apparatus and method for a virtual hashed page table | Feb 2, 1998 | Issued |
Array
(
[id] => 4374133
[patent_doc_number] => 06292878
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-18
[patent_title] => 'Data recorder and method of access to data recorder'
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[patent_app_number] => 9/017675
[patent_app_country] => US
[patent_app_date] => 1998-02-03
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[pdf_file] => patents/06/292/06292878.pdf
[firstpage_image] =>[orig_patent_app_number] => 017675
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/017675 | Data recorder and method of access to data recorder | Feb 2, 1998 | Issued |
Array
(
[id] => 4379586
[patent_doc_number] => 06192450
[patent_country] => US
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[patent_issue_date] => 2001-02-20
[patent_title] => 'Destage of data for write cache'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/018175 | Destage of data for write cache | Feb 2, 1998 | Issued |
Array
(
[id] => 4255108
[patent_doc_number] => 06119209
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[patent_title] => 'Backup directory for a write cache'
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[pdf_file] => patents/06/119/06119209.pdf
[firstpage_image] =>[orig_patent_app_number] => 017830
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/017830 | Backup directory for a write cache | Feb 2, 1998 | Issued |
Array
(
[id] => 4198977
[patent_doc_number] => 06038635
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[patent_issue_date] => 2000-03-14
[patent_title] => 'Microcomputer containing flash EEPROM therein'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/017878 | Microcomputer containing flash EEPROM therein | Feb 2, 1998 | Issued |
Array
(
[id] => 4147535
[patent_doc_number] => 06128706
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[patent_title] => 'Apparatus and method for a load bias--load with intent to semaphore'
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[pdf_file] => patents/06/128/06128706.pdf
[firstpage_image] =>[orig_patent_app_number] => 018165
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/018165 | Apparatus and method for a load bias--load with intent to semaphore | Feb 2, 1998 | Issued |
Array
(
[id] => 4198963
[patent_doc_number] => 06038634
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[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Intra-unit block addressing system for memory'
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[pdf_file] => patents/06/038/06038634.pdf
[firstpage_image] =>[orig_patent_app_number] => 017017
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/017017 | Intra-unit block addressing system for memory | Feb 1, 1998 | Issued |
Array
(
[id] => 4177336
[patent_doc_number] => 06105118
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-15
[patent_title] => 'System and method for selecting which data copy to read in an information handling system'
[patent_app_type] => 1
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[pdf_file] => patents/06/105/06105118.pdf
[firstpage_image] =>[orig_patent_app_number] => 017335
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/017335 | System and method for selecting which data copy to read in an information handling system | Feb 1, 1998 | Issued |
| 09/006404 | BINARY MEMORY DESIGN WITH DATA STORED IN LOW POWER SENSE | Jan 12, 1998 | Abandoned |
Array
(
[id] => 4379500
[patent_doc_number] => 06192444
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[patent_title] => 'Method and system for providing additional addressable functional space on a disk for use with a virtual data storage subsystem'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/002686 | Method and system for providing additional addressable functional space on a disk for use with a virtual data storage subsystem | Jan 4, 1998 | Issued |