Search

Fred Tzeng

Examiner (ID: 5378)

Most Active Art Unit
2627
Art Unit(s)
2186, 2686, 2627, 2752, 2651, 2695, 2625
Total Applications
1789
Issued Applications
1607
Pending Applications
63
Abandoned Applications
139

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4162172 [patent_doc_number] => 06032219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'System and method for buffering data' [patent_app_type] => 1 [patent_app_number] => 8/904638 [patent_app_country] => US [patent_app_date] => 1997-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6419 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032219.pdf [firstpage_image] =>[orig_patent_app_number] => 904638 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904638
System and method for buffering data Jul 31, 1997 Issued
Array ( [id] => 4071712 [patent_doc_number] => 05933856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'System and method for processing of memory data and communication system comprising such system' [patent_app_type] => 1 [patent_app_number] => 8/817508 [patent_app_country] => US [patent_app_date] => 1997-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3039 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933856.pdf [firstpage_image] =>[orig_patent_app_number] => 817508 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/817508
System and method for processing of memory data and communication system comprising such system Jul 8, 1997 Issued
Array ( [id] => 1186337 [patent_doc_number] => 06742080 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'Disk block allocation optimization methodology and application' [patent_app_type] => B1 [patent_app_number] => 08/885325 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 5123 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742080.pdf [firstpage_image] =>[orig_patent_app_number] => 08885325 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885325
Disk block allocation optimization methodology and application Jun 29, 1997 Issued
Array ( [id] => 4371201 [patent_doc_number] => 06216211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method and apparatus for accessing mirrored logical volumes' [patent_app_type] => 1 [patent_app_number] => 8/874531 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4451 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216211.pdf [firstpage_image] =>[orig_patent_app_number] => 874531 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874531
Method and apparatus for accessing mirrored logical volumes Jun 12, 1997 Issued
Array ( [id] => 3973300 [patent_doc_number] => 05978882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Real-mode, 32-bit, flat-model execution apparatus and method' [patent_app_type] => 1 [patent_app_number] => 8/842962 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9099 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978882.pdf [firstpage_image] =>[orig_patent_app_number] => 842962 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/842962
Real-mode, 32-bit, flat-model execution apparatus and method Apr 24, 1997 Issued
Array ( [id] => 4022088 [patent_doc_number] => 05987577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Dual word enable method and apparatus for memory arrays' [patent_app_type] => 1 [patent_app_number] => 8/842523 [patent_app_country] => US [patent_app_date] => 1997-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7218 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987577.pdf [firstpage_image] =>[orig_patent_app_number] => 842523 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/842523
Dual word enable method and apparatus for memory arrays Apr 23, 1997 Issued
Array ( [id] => 4021975 [patent_doc_number] => 05987571 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Cache coherency control method and multi-processor system using the same' [patent_app_type] => 1 [patent_app_number] => 8/839072 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 9560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987571.pdf [firstpage_image] =>[orig_patent_app_number] => 839072 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839072
Cache coherency control method and multi-processor system using the same Apr 22, 1997 Issued
Array ( [id] => 4113838 [patent_doc_number] => 06049810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Method and apparatus for implementing a write barrier of a garbage collected heap' [patent_app_type] => 1 [patent_app_number] => 8/842194 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 32 [patent_no_of_words] => 16846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049810.pdf [firstpage_image] =>[orig_patent_app_number] => 842194 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/842194
Method and apparatus for implementing a write barrier of a garbage collected heap Apr 22, 1997 Issued
Array ( [id] => 4259684 [patent_doc_number] => 06092147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Virtual machine with securely distributed bytecode verification' [patent_app_type] => 1 [patent_app_number] => 8/839621 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5647 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092147.pdf [firstpage_image] =>[orig_patent_app_number] => 839621 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839621
Virtual machine with securely distributed bytecode verification Apr 14, 1997 Issued
Array ( [id] => 4025204 [patent_doc_number] => 06006311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Dynamic updating of repair mask used for cache defect avoidance' [patent_app_type] => 1 [patent_app_number] => 8/839559 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6164 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006311.pdf [firstpage_image] =>[orig_patent_app_number] => 839559 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839559
Dynamic updating of repair mask used for cache defect avoidance Apr 13, 1997 Issued
Array ( [id] => 4177251 [patent_doc_number] => 06105112 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Dynamic folding of cache operations for multiple coherency-size systems' [patent_app_type] => 1 [patent_app_number] => 8/834120 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3954 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105112.pdf [firstpage_image] =>[orig_patent_app_number] => 834120 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/834120
Dynamic folding of cache operations for multiple coherency-size systems Apr 13, 1997 Issued
Array ( [id] => 1549564 [patent_doc_number] => 06374330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Cache-coherency protocol with upstream undefined state' [patent_app_type] => B1 [patent_app_number] => 08/839545 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4540 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374330.pdf [firstpage_image] =>[orig_patent_app_number] => 08839545 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839545
Cache-coherency protocol with upstream undefined state Apr 13, 1997 Issued
Array ( [id] => 7633084 [patent_doc_number] => 06658536 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Cache-coherency protocol with recently read state for extending cache horizontally' [patent_app_type] => B1 [patent_app_number] => 08/839547 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4523 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658536.pdf [firstpage_image] =>[orig_patent_app_number] => 08839547 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839547
Cache-coherency protocol with recently read state for extending cache horizontally Apr 13, 1997 Issued
Array ( [id] => 4317803 [patent_doc_number] => 06182188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method of performing reliable updates in a symmetrically blocked nonvolatile memory having a bifurcated storage architecture' [patent_app_type] => 1 [patent_app_number] => 8/834930 [patent_app_country] => US [patent_app_date] => 1997-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 37 [patent_no_of_words] => 17518 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182188.pdf [firstpage_image] =>[orig_patent_app_number] => 834930 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/834930
Method of performing reliable updates in a symmetrically blocked nonvolatile memory having a bifurcated storage architecture Apr 5, 1997 Issued
Array ( [id] => 626336 [patent_doc_number] => 07139872 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-21 [patent_title] => 'System and method for assessing the effectiveness of a cache memory or portion thereof using FIFO or LRU using cache utilization statistics' [patent_app_type] => utility [patent_app_number] => 08/833410 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7005 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139872.pdf [firstpage_image] =>[orig_patent_app_number] => 08833410 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/833410
System and method for assessing the effectiveness of a cache memory or portion thereof using FIFO or LRU using cache utilization statistics Apr 3, 1997 Issued
Array ( [id] => 4026452 [patent_doc_number] => 05941999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method and system for achieving high availability in networked computer systems' [patent_app_type] => 1 [patent_app_number] => 8/829156 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941999.pdf [firstpage_image] =>[orig_patent_app_number] => 829156 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829156
Method and system for achieving high availability in networked computer systems Mar 30, 1997 Issued
Array ( [id] => 4391595 [patent_doc_number] => 06289418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Address pipelined stack caching method' [patent_app_type] => 1 [patent_app_number] => 8/829105 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 14684 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289418.pdf [firstpage_image] =>[orig_patent_app_number] => 829105 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829105
Address pipelined stack caching method Mar 30, 1997 Issued
Array ( [id] => 4085134 [patent_doc_number] => 06009493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Data transfer control method and apparatus for performing consecutive burst transfer operations with a simple structure' [patent_app_type] => 1 [patent_app_number] => 8/824761 [patent_app_country] => US [patent_app_date] => 1997-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8214 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009493.pdf [firstpage_image] =>[orig_patent_app_number] => 824761 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/824761
Data transfer control method and apparatus for performing consecutive burst transfer operations with a simple structure Mar 25, 1997 Issued
Array ( [id] => 4040716 [patent_doc_number] => 05926833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Method and system allowing direct data access to a shared data storage subsystem by heterogeneous computing systems' [patent_app_type] => 1 [patent_app_number] => 8/822891 [patent_app_country] => US [patent_app_date] => 1997-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926833.pdf [firstpage_image] =>[orig_patent_app_number] => 822891 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/822891
Method and system allowing direct data access to a shared data storage subsystem by heterogeneous computing systems Mar 23, 1997 Issued
Array ( [id] => 4138954 [patent_doc_number] => 06073226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'System and method for minimizing page tables in virtual memory systems' [patent_app_type] => 1 [patent_app_number] => 8/820155 [patent_app_country] => US [patent_app_date] => 1997-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6220 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 28 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073226.pdf [firstpage_image] =>[orig_patent_app_number] => 820155 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/820155
System and method for minimizing page tables in virtual memory systems Mar 18, 1997 Issued
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