Frederick B. Hargrove

Array ( [id] => 12154746 [patent_doc_number] => 20180026010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/215605 [patent_app_country] => US [patent_app_date] => 2016-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15215605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11439272 [patent_doc_number] => 20170040293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'PRINTED CIRCUIT BOARD (PCB), METHOD OF MANUFACTURING THE PCB, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE PCB' [patent_app_type] => utility [patent_app_number] => 15/215583 [patent_app_country] => US [patent_app_date] => 2016-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 16068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15215583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11125391 [patent_doc_number] => 20160322365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING AIR GAP, A METHOD FOR MANUFACTURING THE SAME, A MEMORY CELL HAVING THE SAME AND AN ELECTRONIC DEVICE HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/209502 [patent_app_country] => US [patent_app_date] => 2016-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 56 [patent_no_of_words] => 20331 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11652761 [patent_doc_number] => 20170148662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'SEMICONDUCTOR STRUCTURES INCLUDING MIDDLE-OF-LINE (MOL) CAPACITANCE REDUCTION FOR SELF-ALIGNED CONTACT IN GATE STACK' [patent_app_type] => utility [patent_app_number] => 15/206127 [patent_app_country] => US [patent_app_date] => 2016-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4490 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15206127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13769635 [patent_doc_number] => 10177167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Hybrid substrate engineering in CMOS finFET integration for mobility improvement [patent_app_type] => utility [patent_app_number] => 15/202940 [patent_app_country] => US [patent_app_date] => 2016-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 4390 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15202940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11460008 [patent_doc_number] => 20170053914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 15/193842 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13682573 [patent_doc_number] => 20160380023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => SEMICONDUCTOR OPTICAL DEVICE INTEGRATING PHOTODIODE WITH OPTICAL WAVEGUIDE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/193814 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11753492 [patent_doc_number] => 09711511 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-18 [patent_title] => 'Vertical channel transistor-based semiconductor memory structure' [patent_app_type] => utility [patent_app_number] => 15/193867 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 17 [patent_no_of_words] => 4351 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193867 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13724001 [patent_doc_number] => 20170372956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => SELF-ALIGNED CONTACT [patent_app_type] => utility [patent_app_number] => 15/193831 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13724231 [patent_doc_number] => 20170373071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => VERTICAL CHANNEL TRANSISTOR-BASED SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/193902 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13921789 [patent_doc_number] => 10205019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Semiconductor device having a fin at a side of a semiconductor body [patent_app_type] => utility [patent_app_number] => 15/163428 [patent_app_country] => US [patent_app_date] => 2016-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 5806 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12062059 [patent_doc_number] => 20170338404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'FABRICATING A CAP LAYER FOR A MAGNETIC RANDOM ACCESS MEMORY (MRAM) DEVICE' [patent_app_type] => utility [patent_app_number] => 15/157834 [patent_app_country] => US [patent_app_date] => 2016-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4371 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15157834 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12202449 [patent_doc_number] => 09905521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-27 [patent_title] => 'Method for manufacturing semiconductor light-emitting device and semiconductor light-emitting device' [patent_app_type] => utility [patent_app_number] => 15/157133 [patent_app_country] => US [patent_app_date] => 2016-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 7659 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15157133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11586018 [patent_doc_number] => 09640671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Deep gate-all-around semiconductor device having germanium or group III-V active layer' [patent_app_type] => utility [patent_app_number] => 15/134093 [patent_app_country] => US [patent_app_date] => 2016-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7221 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15134093 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11475629 [patent_doc_number] => 20170062412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'TRANSISTOR ELEMENT AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/132273 [patent_app_country] => US [patent_app_date] => 2016-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4221 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15132273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11681391 [patent_doc_number] => 09679926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Method of manufacturing pixel structure and pixel structure' [patent_app_type] => utility [patent_app_number] => 15/133218 [patent_app_country] => US [patent_app_date] => 2016-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4626 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15133218 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11293756 [patent_doc_number] => 20160343688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE HAVING A MULTI-LAYER MOLDED CONDUCTIVE SUBSTRATE AND STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/133081 [patent_app_country] => US [patent_app_date] => 2016-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15133081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11125529 [patent_doc_number] => 20160322503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/131298 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 62 [patent_no_of_words] => 42540 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15131298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11983901 [patent_doc_number] => 20170288057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'KITE SHAPED CAVITY FOR EMBEDDING MATERIAL' [patent_app_type] => utility [patent_app_number] => 15/131021 [patent_app_country] => US [patent_app_date] => 2016-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15131021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11645307 [patent_doc_number] => 09666701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-30 [patent_title] => 'Integrated circuit heat dissipation using nanostructures' [patent_app_type] => utility [patent_app_number] => 15/074165 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6210 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15074165 [rel_patent_id] =>[rel_patent_doc_number] =>)