Search

Fritz Alphonse

Examiner (ID: 6631)

Most Active Art Unit
2112
Art Unit(s)
2675, 2133, 2112, 2775
Total Applications
1754
Issued Applications
1609
Pending Applications
27
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7429303 [patent_doc_number] => 20040209449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Method of characterizing implantation of species in a substrate' [patent_app_type] => new [patent_app_number] => 10/809918 [patent_app_country] => US [patent_app_date] => 2004-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3683 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20040209449.pdf [firstpage_image] =>[orig_patent_app_number] => 10809918 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/809918
Method of characterizing implantation of a species in a substrate by surface imaging Mar 25, 2004 Issued
Array ( [id] => 7260419 [patent_doc_number] => 20040150105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Contact structure for reliable metallic interconnection' [patent_app_type] => new [patent_app_number] => 10/762163 [patent_app_country] => US [patent_app_date] => 2004-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4294 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20040150105.pdf [firstpage_image] =>[orig_patent_app_number] => 10762163 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/762163
Contact structure for reliable metallic interconnection Jan 19, 2004 Abandoned
Array ( [id] => 7324103 [patent_doc_number] => 20040137648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Ferroelectric memory device and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/744378 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3706 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20040137648.pdf [firstpage_image] =>[orig_patent_app_number] => 10744378 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/744378
Method of fabricating a ferroelectric memory device Dec 21, 2003 Issued
Array ( [id] => 1031049 [patent_doc_number] => 06878601 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-12 [patent_title] => 'Method for fabricating a capacitor containing metastable polysilicon' [patent_app_type] => utility [patent_app_number] => 10/742138 [patent_app_country] => US [patent_app_date] => 2003-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 1784 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/878/06878601.pdf [firstpage_image] =>[orig_patent_app_number] => 10742138 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/742138
Method for fabricating a capacitor containing metastable polysilicon Dec 18, 2003 Issued
Array ( [id] => 1096062 [patent_doc_number] => 06821880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Process of dual or single damascene utilizing separate etching and DCM apparati' [patent_app_type] => B1 [patent_app_number] => 10/725138 [patent_app_country] => US [patent_app_date] => 2003-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1516 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821880.pdf [firstpage_image] =>[orig_patent_app_number] => 10725138 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/725138
Process of dual or single damascene utilizing separate etching and DCM apparati Nov 30, 2003 Issued
Array ( [id] => 7309278 [patent_doc_number] => 20040142540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Wafer bonding for three-dimensional (3D) integration' [patent_app_type] => new [patent_app_number] => 10/695328 [patent_app_country] => US [patent_app_date] => 2003-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20040142540.pdf [firstpage_image] =>[orig_patent_app_number] => 10695328 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/695328
Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration Oct 26, 2003 Issued
Array ( [id] => 1151742 [patent_doc_number] => 06767761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-27 [patent_title] => 'Method of manufacturing a flip-chip semiconductor device with a stress-absorbing layer made of thermosetting resin' [patent_app_type] => B2 [patent_app_number] => 10/686568 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 96 [patent_no_of_words] => 7559 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/767/06767761.pdf [firstpage_image] =>[orig_patent_app_number] => 10686568 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/686568
Method of manufacturing a flip-chip semiconductor device with a stress-absorbing layer made of thermosetting resin Oct 16, 2003 Issued
Array ( [id] => 7131830 [patent_doc_number] => 20040042283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Multilayered doped conductor' [patent_app_type] => new [patent_app_number] => 10/650563 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7203 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20040042283.pdf [firstpage_image] =>[orig_patent_app_number] => 10650563 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/650563
Method of manufacturing a multilayered doped conductor for a contact in an integrated device Aug 27, 2003 Issued
Array ( [id] => 1017898 [patent_doc_number] => 06890792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Method of formation of a capacitor with a solid electrolyte layer comprising an organic semiconductor, and method of production of circuit board' [patent_app_type] => utility [patent_app_number] => 10/645478 [patent_app_country] => US [patent_app_date] => 2003-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 36 [patent_no_of_words] => 6048 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/890/06890792.pdf [firstpage_image] =>[orig_patent_app_number] => 10645478 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/645478
Method of formation of a capacitor with a solid electrolyte layer comprising an organic semiconductor, and method of production of circuit board Aug 21, 2003 Issued
Array ( [id] => 1111015 [patent_doc_number] => 06806176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Semiconductor device and method of manufacturing the same, circuit board and electronic instrument' [patent_app_type] => B2 [patent_app_number] => 10/623498 [patent_app_country] => US [patent_app_date] => 2003-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 32 [patent_no_of_words] => 7778 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806176.pdf [firstpage_image] =>[orig_patent_app_number] => 10623498 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/623498
Semiconductor device and method of manufacturing the same, circuit board and electronic instrument Jul 21, 2003 Issued
Array ( [id] => 7465603 [patent_doc_number] => 20040053513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Method for production of semiconductor components' [patent_app_type] => new [patent_app_number] => 10/625118 [patent_app_country] => US [patent_app_date] => 2003-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2222 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20040053513.pdf [firstpage_image] =>[orig_patent_app_number] => 10625118 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/625118
Method of semiconductor processing including fluoride Jul 21, 2003 Issued
Array ( [id] => 1155467 [patent_doc_number] => 06764889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Methods of forming vertical mosfets having trench-based gate electrodes within deeper trench-based source electrodes' [patent_app_type] => B2 [patent_app_number] => 10/621668 [patent_app_country] => US [patent_app_date] => 2003-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 13057 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/764/06764889.pdf [firstpage_image] =>[orig_patent_app_number] => 10621668 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/621668
Methods of forming vertical mosfets having trench-based gate electrodes within deeper trench-based source electrodes Jul 16, 2003 Issued
Array ( [id] => 7450481 [patent_doc_number] => 20040067656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Method for forming bit line of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/608808 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2437 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20040067656.pdf [firstpage_image] =>[orig_patent_app_number] => 10608808 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608808
Method for forming bit line of semiconductor device Jun 29, 2003 Issued
Array ( [id] => 7328823 [patent_doc_number] => 20040253752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'METHOD AND SYSTEM FOR MONITORING IMPLANTATION OF IONS INTO SEMICONDUCTOR SUBSTRATES' [patent_app_type] => new [patent_app_number] => 10/462028 [patent_app_country] => US [patent_app_date] => 2003-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20040253752.pdf [firstpage_image] =>[orig_patent_app_number] => 10462028 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/462028
Method and system for monitoring implantation of ions into semiconductor substrates Jun 11, 2003 Issued
Array ( [id] => 1085666 [patent_doc_number] => 06831012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'Method for forming a silicide film of a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/445858 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831012.pdf [firstpage_image] =>[orig_patent_app_number] => 10445858 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445858
Method for forming a silicide film of a semiconductor device May 27, 2003 Issued
Array ( [id] => 6807295 [patent_doc_number] => 20030197234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Low dielectric constant shallow trench isolation' [patent_app_type] => new [patent_app_number] => 10/435171 [patent_app_country] => US [patent_app_date] => 2003-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7513 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20030197234.pdf [firstpage_image] =>[orig_patent_app_number] => 10435171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435171
Low dielectric constant shallow trench isolation May 7, 2003 Issued
Array ( [id] => 7365758 [patent_doc_number] => 20040005768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Method of making an icosahedral boride structure' [patent_app_type] => new [patent_app_number] => 10/418018 [patent_app_country] => US [patent_app_date] => 2003-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2466 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20040005768.pdf [firstpage_image] =>[orig_patent_app_number] => 10418018 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/418018
Method of making an icosahedral boride structure Apr 16, 2003 Issued
Array ( [id] => 7629883 [patent_doc_number] => 06818473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Method for fabricating ceramic chip packages' [patent_app_type] => B2 [patent_app_number] => 10/394228 [patent_app_country] => US [patent_app_date] => 2003-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4480 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818473.pdf [firstpage_image] =>[orig_patent_app_number] => 10394228 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/394228
Method for fabricating ceramic chip packages Mar 23, 2003 Issued
Array ( [id] => 6664268 [patent_doc_number] => 20030203594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Non-volatile semiconductor memory device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/393944 [patent_app_country] => US [patent_app_date] => 2003-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 18171 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20030203594.pdf [firstpage_image] =>[orig_patent_app_number] => 10393944 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/393944
Non-volatile semiconductor memory device and manufacturing method thereof Mar 23, 2003 Issued
Array ( [id] => 1095799 [patent_doc_number] => 06821791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method for reworking metal layers on integrated circuit bond pads' [patent_app_type] => B2 [patent_app_number] => 10/375204 [patent_app_country] => US [patent_app_date] => 2003-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 4314 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821791.pdf [firstpage_image] =>[orig_patent_app_number] => 10375204 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/375204
Method for reworking metal layers on integrated circuit bond pads Feb 26, 2003 Issued
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