Search

Fritz Alphonse

Examiner (ID: 313, Phone: (571)272-3813 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2112, 2775, 2133, 2675
Total Applications
1754
Issued Applications
1609
Pending Applications
27
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16667161 [patent_doc_number] => 10936407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => System and method to reduce address range scrub execution time in non-volatile dual inline memory modules [patent_app_type] => utility [patent_app_number] => 16/426372 [patent_app_country] => US [patent_app_date] => 2019-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16426372 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/426372
System and method to reduce address range scrub execution time in non-volatile dual inline memory modules May 29, 2019 Issued
Array ( [id] => 14842649 [patent_doc_number] => 20190279725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/423505 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423505 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/423505
Storage device May 27, 2019 Issued
Array ( [id] => 16480803 [patent_doc_number] => 10855769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Prioritizing memory devices to replace based on namespace health [patent_app_type] => utility [patent_app_number] => 16/416363 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416363 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/416363
Prioritizing memory devices to replace based on namespace health May 19, 2019 Issued
Array ( [id] => 15777473 [patent_doc_number] => 20200119754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => ERROR CORRECTION CIRCUIT, AND MEMORY CONTROLLER HAVING THE ERROR CORRECTION CIRCUIT AND MEMORY SYSTEM HAVING THE MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 16/417208 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417208 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/417208
Error correction circuit, and memory controller having the error correction circuit and memory system having the memory controller May 19, 2019 Issued
Array ( [id] => 15842727 [patent_doc_number] => 20200136646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => DECODING METHOD FOR LOW-DENSITY PARITY-CHECK CODE AND SYSTEM THEREOF [patent_app_type] => utility [patent_app_number] => 16/410511 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16410511 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/410511
Decoding method for low-density parity-check code and system thereof May 12, 2019 Issued
Array ( [id] => 16373163 [patent_doc_number] => 10804937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 16-symbol mapping, and bit interleaving method using same [patent_app_type] => utility [patent_app_number] => 16/395117 [patent_app_country] => US [patent_app_date] => 2019-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6586 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16395117 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/395117
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 16-symbol mapping, and bit interleaving method using same Apr 24, 2019 Issued
Array ( [id] => 16708426 [patent_doc_number] => 10958375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Transmitting apparatus and signal processing method thereof [patent_app_type] => utility [patent_app_number] => 16/376696 [patent_app_country] => US [patent_app_date] => 2019-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 55947 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16376696 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/376696
Transmitting apparatus and signal processing method thereof Apr 4, 2019 Issued
Array ( [id] => 16232633 [patent_doc_number] => 10740183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-11 [patent_title] => Recovering failed devices in distributed data centers [patent_app_type] => utility [patent_app_number] => 16/371933 [patent_app_country] => US [patent_app_date] => 2019-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 32 [patent_no_of_words] => 12912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371933 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/371933
Recovering failed devices in distributed data centers Mar 31, 2019 Issued
Array ( [id] => 14627507 [patent_doc_number] => 20190227121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => APPARATUS FOR MEMORY BUILT-IN SELF-TEST WITH ERROR DETECTION AND CORRECTION CODE AWARENESS [patent_app_type] => utility [patent_app_number] => 16/370993 [patent_app_country] => US [patent_app_date] => 2019-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370993 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370993
Apparatus for memory built-in self-test with error detection and correction code awareness Mar 29, 2019 Issued
Array ( [id] => 14585493 [patent_doc_number] => 20190220355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => PROCESSING DATA ACCESS TRANSACTIONS IN A DISPERSED STORAGE NETWORK USING SOURCE REVISION INDICATORS [patent_app_type] => utility [patent_app_number] => 16/366979 [patent_app_country] => US [patent_app_date] => 2019-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16366979 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/366979
Processing data access transactions in a dispersed storage network using source revision indicators Mar 26, 2019 Issued
Array ( [id] => 16520798 [patent_doc_number] => 10872013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Non volatile memory controller device and method for adjustment [patent_app_type] => utility [patent_app_number] => 16/354526 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6424 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16354526 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/354526
Non volatile memory controller device and method for adjustment Mar 14, 2019 Issued
Array ( [id] => 14872561 [patent_doc_number] => 20190286522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => LDPC DECODING DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/355296 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16355296 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/355296
LDPC decoding device, memory system including the same and method thereof Mar 14, 2019 Issued
Array ( [id] => 15297471 [patent_doc_number] => 20190391871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => BYPASSING ERROR CORRECTION CODE (ECC) PROCESSING BASED ON SOFTWARE HINT [patent_app_type] => utility [patent_app_number] => 16/284912 [patent_app_country] => US [patent_app_date] => 2019-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16284912 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/284912
Bypassing error correction code (ECC) processing based on software hint Feb 24, 2019 Issued
Array ( [id] => 14443321 [patent_doc_number] => 20190179533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => Proactive Data Rebuild Based On Queue Feedback [patent_app_type] => utility [patent_app_number] => 16/278547 [patent_app_country] => US [patent_app_date] => 2019-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16278547 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/278547
Proactive data rebuild based on queue feedback Feb 17, 2019 Issued
Array ( [id] => 14589237 [patent_doc_number] => 20190222227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => METHOD AND APPARATUS OF A FULLY-PIPELINED LAYERED LDPC DECODER [patent_app_type] => utility [patent_app_number] => 16/277890 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9368 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16277890 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/277890
Method and apparatus of a fully-pipelined layered LDPC decoder Feb 14, 2019 Issued
Array ( [id] => 16478219 [patent_doc_number] => 10853167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Memory apparatus having hierarchical error correction code layer [patent_app_type] => utility [patent_app_number] => 16/260058 [patent_app_country] => US [patent_app_date] => 2019-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2573 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16260058 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/260058
Memory apparatus having hierarchical error correction code layer Jan 27, 2019 Issued
Array ( [id] => 16478216 [patent_doc_number] => 10853164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Display and display system [patent_app_type] => utility [patent_app_number] => 16/259402 [patent_app_country] => US [patent_app_date] => 2019-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7921 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16259402 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/259402
Display and display system Jan 27, 2019 Issued
Array ( [id] => 14347075 [patent_doc_number] => 20190155510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => EXPANDING A DISPERSED STORAGE NETWORK (DSN) [patent_app_type] => utility [patent_app_number] => 16/256195 [patent_app_country] => US [patent_app_date] => 2019-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16256195 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/256195
Expanding a dispersed storage network (DSN) Jan 23, 2019 Issued
Array ( [id] => 16294233 [patent_doc_number] => 10771091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Flash memory apparatus and storage management method for flash memory [patent_app_type] => utility [patent_app_number] => 16/251033 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10193 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16251033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/251033
Flash memory apparatus and storage management method for flash memory Jan 16, 2019 Issued
Array ( [id] => 16339890 [patent_doc_number] => 10790862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Cache index mapping [patent_app_type] => utility [patent_app_number] => 16/241275 [patent_app_country] => US [patent_app_date] => 2019-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241275 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/241275
Cache index mapping Jan 6, 2019 Issued
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