Search

Fritz Alphonse

Examiner (ID: 6631)

Most Active Art Unit
2112
Art Unit(s)
2675, 2133, 2112, 2775
Total Applications
1754
Issued Applications
1609
Pending Applications
27
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1545297 [patent_doc_number] => 06444554 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method of making a non-volatile memory and semiconductor device' [patent_app_type] => B1 [patent_app_number] => 10/011731 [patent_app_country] => US [patent_app_date] => 2001-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 126 [patent_no_of_words] => 32560 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/444/06444554.pdf [firstpage_image] =>[orig_patent_app_number] => 10011731 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/011731
Method of making a non-volatile memory and semiconductor device Dec 10, 2001 Issued
Array ( [id] => 1375685 [patent_doc_number] => 06559010 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method for forming embedded non-volatile memory' [patent_app_type] => B1 [patent_app_number] => 10/003320 [patent_app_country] => US [patent_app_date] => 2001-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3274 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559010.pdf [firstpage_image] =>[orig_patent_app_number] => 10003320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003320
Method for forming embedded non-volatile memory Dec 5, 2001 Issued
Array ( [id] => 1417035 [patent_doc_number] => 06509282 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Silicon-starved PECVD method for metal gate electrode dielectric spacer' [patent_app_type] => B1 [patent_app_number] => 09/994128 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509282.pdf [firstpage_image] =>[orig_patent_app_number] => 09994128 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/994128
Silicon-starved PECVD method for metal gate electrode dielectric spacer Nov 25, 2001 Issued
Array ( [id] => 5936155 [patent_doc_number] => 20020061623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Semiconductor trench device with enhanced gate oxide integrity structure' [patent_app_type] => new [patent_app_number] => 10/042558 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4951 [patent_no_of_claims] => 91 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20020061623.pdf [firstpage_image] =>[orig_patent_app_number] => 10042558 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/042558
Semiconductor trench device with enhanced gate oxide integrity structure Nov 19, 2001 Issued
Array ( [id] => 1507438 [patent_doc_number] => 06440838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Dual damascene structure employing laminated intermediate etch stop layer' [patent_app_type] => B1 [patent_app_number] => 09/996458 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 6596 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440838.pdf [firstpage_image] =>[orig_patent_app_number] => 09996458 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996458
Dual damascene structure employing laminated intermediate etch stop layer Nov 19, 2001 Issued
Array ( [id] => 1273933 [patent_doc_number] => 06649493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Method for fabricating a III nitride film, and underlayer for fabricating a III nitride film and a method for fabricating the same underlayer' [patent_app_type] => B2 [patent_app_number] => 10/044778 [patent_app_country] => US [patent_app_date] => 2001-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4183 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649493.pdf [firstpage_image] =>[orig_patent_app_number] => 10044778 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044778
Method for fabricating a III nitride film, and underlayer for fabricating a III nitride film and a method for fabricating the same underlayer Nov 6, 2001 Issued
Array ( [id] => 6870162 [patent_doc_number] => 20030082851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Back-side through-hole interconnection of a die to a substrate' [patent_app_type] => new [patent_app_number] => 10/000008 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4465 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20030082851.pdf [firstpage_image] =>[orig_patent_app_number] => 10000008 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/000008
Back-side through-hole interconnection of a die to a substrate Oct 30, 2001 Issued
Array ( [id] => 1517379 [patent_doc_number] => 06500761 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method for improving the adhesion and durability of CVD tantalum and tantalum nitride modulated films by plasma treatment' [patent_app_type] => B1 [patent_app_number] => 10/000548 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6696 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500761.pdf [firstpage_image] =>[orig_patent_app_number] => 10000548 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/000548
Method for improving the adhesion and durability of CVD tantalum and tantalum nitride modulated films by plasma treatment Oct 23, 2001 Issued
Array ( [id] => 1395192 [patent_doc_number] => 06541396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Method of manufacturing a semiconductor device using a low dielectric constant organic film grown in a vacuum above an inlaid interconnection layer' [patent_app_type] => B2 [patent_app_number] => 09/983378 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 12513 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541396.pdf [firstpage_image] =>[orig_patent_app_number] => 09983378 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/983378
Method of manufacturing a semiconductor device using a low dielectric constant organic film grown in a vacuum above an inlaid interconnection layer Oct 23, 2001 Issued
Array ( [id] => 1366571 [patent_doc_number] => 06566169 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method and apparatus for local vectorial particle cleaning' [patent_app_type] => B1 [patent_app_number] => 09/869058 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4239 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566169.pdf [firstpage_image] =>[orig_patent_app_number] => 09869058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/869058
Method and apparatus for local vectorial particle cleaning Oct 15, 2001 Issued
Array ( [id] => 1332260 [patent_doc_number] => 06596589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Method of manufacturing a high coupling ratio stacked gate flash memory with an HSG-SI layer' [patent_app_type] => B2 [patent_app_number] => 09/976446 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2770 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/596/06596589.pdf [firstpage_image] =>[orig_patent_app_number] => 09976446 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976446
Method of manufacturing a high coupling ratio stacked gate flash memory with an HSG-SI layer Oct 11, 2001 Issued
Array ( [id] => 6657332 [patent_doc_number] => 20030077921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Carbon doped oxide deposition' [patent_app_type] => new [patent_app_number] => 09/972228 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20030077921.pdf [firstpage_image] =>[orig_patent_app_number] => 09972228 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/972228
Carbon doped oxide deposition Oct 4, 2001 Issued
Array ( [id] => 5801645 [patent_doc_number] => 20020009858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => ' Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same' [patent_app_type] => new [patent_app_number] => 09/963842 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5484 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20020009858.pdf [firstpage_image] =>[orig_patent_app_number] => 09963842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/963842
Method for fabricating a memory chip Sep 24, 2001 Issued
Array ( [id] => 6063527 [patent_doc_number] => 20020031857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Vertically mountable semiconductor device and methods' [patent_app_type] => new [patent_app_number] => 09/944510 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2760 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20020031857.pdf [firstpage_image] =>[orig_patent_app_number] => 09944510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/944510
Vertically mountable semiconductor device and methods Aug 29, 2001 Abandoned
Array ( [id] => 6405996 [patent_doc_number] => 20020037638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Semiconductor device and method for forming the same' [patent_app_type] => new [patent_app_number] => 09/938538 [patent_app_country] => US [patent_app_date] => 2001-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2175 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20020037638.pdf [firstpage_image] =>[orig_patent_app_number] => 09938538 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/938538
Method for manufacturing a semiconductor device with a dual interlayer insulator film of borophosphosilicate glass to prevent diffusion of phosphorus Aug 26, 2001 Issued
Array ( [id] => 6095974 [patent_doc_number] => 20020052122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 09/931938 [patent_app_country] => US [patent_app_date] => 2001-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 17713 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20020052122.pdf [firstpage_image] =>[orig_patent_app_number] => 09931938 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/931938
Manufacturing use of photomasks with an opaque pattern comprising an organic layer photoabsorptive to exposure light with wavelengths exceeding 200 NM Aug 19, 2001 Issued
Array ( [id] => 1381954 [patent_doc_number] => 06551896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'Capacitor for analog circuit, and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 09/913768 [patent_app_country] => US [patent_app_date] => 2001-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5580 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/551/06551896.pdf [firstpage_image] =>[orig_patent_app_number] => 09913768 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/913768
Capacitor for analog circuit, and manufacturing method thereof Aug 15, 2001 Issued
Array ( [id] => 1424734 [patent_doc_number] => 06503851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-07 [patent_title] => 'Use of linear injectors to deposit uniform selective ozone TEOS oxide film by pulsing reactants on and off' [patent_app_type] => B2 [patent_app_number] => 09/921539 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5555 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/503/06503851.pdf [firstpage_image] =>[orig_patent_app_number] => 09921539 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/921539
Use of linear injectors to deposit uniform selective ozone TEOS oxide film by pulsing reactants on and off Aug 2, 2001 Issued
Array ( [id] => 1209323 [patent_doc_number] => 06713364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method for forming an insulator having a low dielectric constant on a semiconductor substrate' [patent_app_type] => B2 [patent_app_number] => 09/918428 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1358 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713364.pdf [firstpage_image] =>[orig_patent_app_number] => 09918428 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/918428
Method for forming an insulator having a low dielectric constant on a semiconductor substrate Jul 26, 2001 Issued
Array ( [id] => 1390003 [patent_doc_number] => 06544847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Single poly non-volatile memory structure and its fabricating method' [patent_app_type] => B2 [patent_app_number] => 09/915928 [patent_app_country] => US [patent_app_date] => 2001-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2831 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544847.pdf [firstpage_image] =>[orig_patent_app_number] => 09915928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915928
Single poly non-volatile memory structure and its fabricating method Jul 25, 2001 Issued
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