
Fritz Alphonse
Examiner (ID: 6631)
| Most Active Art Unit | 2112 |
| Art Unit(s) | 2675, 2133, 2112, 2775 |
| Total Applications | 1754 |
| Issued Applications | 1609 |
| Pending Applications | 27 |
| Abandoned Applications | 125 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1545297
[patent_doc_number] => 06444554
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-03
[patent_title] => 'Method of making a non-volatile memory and semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 10/011731
[patent_app_country] => US
[patent_app_date] => 2001-12-11
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[pdf_file] => patents/06/444/06444554.pdf
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Array
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[patent_issue_date] => 2003-05-06
[patent_title] => 'Method for forming embedded non-volatile memory'
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Array
(
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[patent_issue_date] => 2003-01-21
[patent_title] => 'Silicon-starved PECVD method for metal gate electrode dielectric spacer'
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[patent_app_number] => 09/994128
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Array
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[patent_issue_date] => 2002-05-23
[patent_title] => 'Semiconductor trench device with enhanced gate oxide integrity structure'
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Array
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[patent_title] => 'Dual damascene structure employing laminated intermediate etch stop layer'
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Array
(
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[patent_issue_date] => 2003-11-18
[patent_title] => 'Method for fabricating a III nitride film, and underlayer for fabricating a III nitride film and a method for fabricating the same underlayer'
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Array
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[patent_title] => 'Back-side through-hole interconnection of a die to a substrate'
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Array
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[patent_issue_date] => 2002-12-31
[patent_title] => 'Method for improving the adhesion and durability of CVD tantalum and tantalum nitride modulated films by plasma treatment'
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[patent_app_number] => 10/000548
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Array
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[patent_title] => 'Method of manufacturing a semiconductor device using a low dielectric constant organic film grown in a vacuum above an inlaid interconnection layer'
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Array
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[patent_title] => 'Method and apparatus for local vectorial particle cleaning'
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Array
(
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[patent_title] => 'Method of manufacturing a high coupling ratio stacked gate flash memory with an HSG-SI layer'
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Array
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Array
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Array
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Array
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Array
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Array
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