
Gabriele E. Bugaisky
Examiner (ID: 12390)
| Most Active Art Unit | 1653 |
| Art Unit(s) | 2899, 1653, 1643, 1609, 1654, 2900, 1634, 1804, 1814, 1652, 1656 |
| Total Applications | 617 |
| Issued Applications | 349 |
| Pending Applications | 104 |
| Abandoned Applications | 164 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3987745
[patent_doc_number] => 05905764
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'Radio receiver'
[patent_app_type] => 1
[patent_app_number] => 8/796068
[patent_app_country] => US
[patent_app_date] => 1997-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6011
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/905/05905764.pdf
[firstpage_image] =>[orig_patent_app_number] => 796068
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/796068 | Radio receiver | Feb 3, 1997 | Issued |
Array
(
[id] => 3959705
[patent_doc_number] => 05982835
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Digital processing phase lock loop for synchronous digital micro-wave apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/789233
[patent_app_country] => US
[patent_app_date] => 1997-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1979
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/982/05982835.pdf
[firstpage_image] =>[orig_patent_app_number] => 789233
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/789233 | Digital processing phase lock loop for synchronous digital micro-wave apparatus | Feb 3, 1997 | Issued |
Array
(
[id] => 4079399
[patent_doc_number] => 05867545
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-02
[patent_title] => 'Phase-locked loop circuit'
[patent_app_type] => 1
[patent_app_number] => 8/794467
[patent_app_country] => US
[patent_app_date] => 1997-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6202
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/867/05867545.pdf
[firstpage_image] =>[orig_patent_app_number] => 794467
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/794467 | Phase-locked loop circuit | Feb 3, 1997 | Issued |
Array
(
[id] => 3804098
[patent_doc_number] => 05841810
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Multiple stage adaptive equalizer'
[patent_app_type] => 1
[patent_app_number] => 8/791382
[patent_app_country] => US
[patent_app_date] => 1997-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2539
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 302
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/841/05841810.pdf
[firstpage_image] =>[orig_patent_app_number] => 791382
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/791382 | Multiple stage adaptive equalizer | Jan 29, 1997 | Issued |
Array
(
[id] => 3916982
[patent_doc_number] => 05898734
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-27
[patent_title] => 'Symbol determining method and apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/790751
[patent_app_country] => US
[patent_app_date] => 1997-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 4575
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/898/05898734.pdf
[firstpage_image] =>[orig_patent_app_number] => 790751
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/790751 | Symbol determining method and apparatus | Jan 26, 1997 | Issued |
Array
(
[id] => 4066522
[patent_doc_number] => 05970093
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Fractionally-spaced adaptively-equalized self-recovering digital receiver for amplitude-Phase modulated signals'
[patent_app_type] => 1
[patent_app_number] => 8/784607
[patent_app_country] => US
[patent_app_date] => 1997-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 68
[patent_no_of_words] => 16506
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/970/05970093.pdf
[firstpage_image] =>[orig_patent_app_number] => 784607
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/784607 | Fractionally-spaced adaptively-equalized self-recovering digital receiver for amplitude-Phase modulated signals | Jan 20, 1997 | Issued |
Array
(
[id] => 4021080
[patent_doc_number] => 05889829
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Phase locked loop with improved lock time and stability'
[patent_app_type] => 1
[patent_app_number] => 8/779907
[patent_app_country] => US
[patent_app_date] => 1997-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2837
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/889/05889829.pdf
[firstpage_image] =>[orig_patent_app_number] => 779907
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/779907 | Phase locked loop with improved lock time and stability | Jan 6, 1997 | Issued |
Array
(
[id] => 3972599
[patent_doc_number] => 05901190
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-04
[patent_title] => 'Digital delay locked loop circuit using synchronous delay line'
[patent_app_type] => 1
[patent_app_number] => 8/771538
[patent_app_country] => US
[patent_app_date] => 1996-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3420
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/901/05901190.pdf
[firstpage_image] =>[orig_patent_app_number] => 771538
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/771538 | Digital delay locked loop circuit using synchronous delay line | Dec 22, 1996 | Issued |
Array
(
[id] => 4012403
[patent_doc_number] => 05923715
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Digital phase-locked loop circuit'
[patent_app_type] => 1
[patent_app_number] => 8/772008
[patent_app_country] => US
[patent_app_date] => 1996-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 7648
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/923/05923715.pdf
[firstpage_image] =>[orig_patent_app_number] => 772008
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/772008 | Digital phase-locked loop circuit | Dec 18, 1996 | Issued |
Array
(
[id] => 4055523
[patent_doc_number] => 05909474
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-01
[patent_title] => 'Phase-locked loop system'
[patent_app_type] => 1
[patent_app_number] => 8/768633
[patent_app_country] => US
[patent_app_date] => 1996-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 17
[patent_no_of_words] => 5702
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/909/05909474.pdf
[firstpage_image] =>[orig_patent_app_number] => 768633
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/768633 | Phase-locked loop system | Dec 17, 1996 | Issued |
Array
(
[id] => 4068535
[patent_doc_number] => 05864586
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-26
[patent_title] => 'Radio apparatus with offset compensating circuit'
[patent_app_type] => 1
[patent_app_number] => 8/768354
[patent_app_country] => US
[patent_app_date] => 1996-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 6766
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/864/05864586.pdf
[firstpage_image] =>[orig_patent_app_number] => 768354
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/768354 | Radio apparatus with offset compensating circuit | Dec 16, 1996 | Issued |
Array
(
[id] => 3855135
[patent_doc_number] => 05848106
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'Receiver decoder circuitry, and associated method, for decoding an encoded signal'
[patent_app_type] => 1
[patent_app_number] => 8/767542
[patent_app_country] => US
[patent_app_date] => 1996-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4751
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/848/05848106.pdf
[firstpage_image] =>[orig_patent_app_number] => 767542
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/767542 | Receiver decoder circuitry, and associated method, for decoding an encoded signal | Dec 15, 1996 | Issued |
| 08/750577 | MODULATOR/DEMODULATOR ARRANGEMENT FOR DATA TRANSMISSION IN A RADIO COMMUNICATION SYSTEM | Dec 10, 1996 | Abandoned |
Array
(
[id] => 3990078
[patent_doc_number] => 05917857
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-29
[patent_title] => 'Digital modulation apparatus, a digital modulation method, and a recording medium therefor'
[patent_app_type] => 1
[patent_app_number] => 8/764024
[patent_app_country] => US
[patent_app_date] => 1996-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 10309
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 285
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/917/05917857.pdf
[firstpage_image] =>[orig_patent_app_number] => 764024
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/764024 | Digital modulation apparatus, a digital modulation method, and a recording medium therefor | Dec 10, 1996 | Issued |
Array
(
[id] => 3890586
[patent_doc_number] => 05764707
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Method and apparatus for improved phase shift keyed (PSK) signal demodulation'
[patent_app_type] => 1
[patent_app_number] => 8/762642
[patent_app_country] => US
[patent_app_date] => 1996-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6603
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/764/05764707.pdf
[firstpage_image] =>[orig_patent_app_number] => 762642
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/762642 | Method and apparatus for improved phase shift keyed (PSK) signal demodulation | Dec 8, 1996 | Issued |
Array
(
[id] => 3826990
[patent_doc_number] => 05812611
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Frequency estimating circuit and AFC circuit using the same'
[patent_app_type] => 1
[patent_app_number] => 8/760236
[patent_app_country] => US
[patent_app_date] => 1996-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 49
[patent_no_of_words] => 12390
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/812/05812611.pdf
[firstpage_image] =>[orig_patent_app_number] => 760236
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/760236 | Frequency estimating circuit and AFC circuit using the same | Dec 4, 1996 | Issued |
Array
(
[id] => 3855089
[patent_doc_number] => 05848104
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'Demodulator of receiver used for communications'
[patent_app_type] => 1
[patent_app_number] => 8/760566
[patent_app_country] => US
[patent_app_date] => 1996-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 9154
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/848/05848104.pdf
[firstpage_image] =>[orig_patent_app_number] => 760566
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/760566 | Demodulator of receiver used for communications | Dec 3, 1996 | Issued |
Array
(
[id] => 3890392
[patent_doc_number] => 05764695
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Adaptive line equalizer'
[patent_app_type] => 1
[patent_app_number] => 8/756734
[patent_app_country] => US
[patent_app_date] => 1996-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 11674
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/764/05764695.pdf
[firstpage_image] =>[orig_patent_app_number] => 756734
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/756734 | Adaptive line equalizer | Nov 25, 1996 | Issued |
Array
(
[id] => 3785342
[patent_doc_number] => 05774502
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Fully integrated data receiver and method for receiving on/off keyed AM/PDSK modulated signals'
[patent_app_type] => 1
[patent_app_number] => 8/752028
[patent_app_country] => US
[patent_app_date] => 1996-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1794
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/774/05774502.pdf
[firstpage_image] =>[orig_patent_app_number] => 752028
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/752028 | Fully integrated data receiver and method for receiving on/off keyed AM/PDSK modulated signals | Nov 18, 1996 | Issued |
Array
(
[id] => 3868769
[patent_doc_number] => 05706308
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-06
[patent_title] => 'Signal processing apparatus and method for sigma-delta modulated signals including gain adjustment'
[patent_app_type] => 1
[patent_app_number] => 8/753004
[patent_app_country] => US
[patent_app_date] => 1996-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2812
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/706/05706308.pdf
[firstpage_image] =>[orig_patent_app_number] => 753004
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/753004 | Signal processing apparatus and method for sigma-delta modulated signals including gain adjustment | Nov 18, 1996 | Issued |