Search

Gary Chin

Examiner (ID: 1842)

Most Active Art Unit
2304
Art Unit(s)
2306, 2304, 2307, 3661, 2763, 3614, 2203
Total Applications
2057
Issued Applications
1788
Pending Applications
41
Abandoned Applications
228

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17165964 [patent_doc_number] => 11152072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Memory device including grouped page buffers and read operation method thereof [patent_app_type] => utility [patent_app_number] => 16/662900 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16662900 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/662900
Memory device including grouped page buffers and read operation method thereof Oct 23, 2019 Issued
Array ( [id] => 16780420 [patent_doc_number] => 20210117499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => METHODS TO TOLERATE PROGRAMMING AND RETENTION ERRORS OF CROSSBAR MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 16/655575 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655575 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/655575
Methods to tolerate programming and retention errors of crossbar memory arrays Oct 16, 2019 Issued
Array ( [id] => 16256541 [patent_doc_number] => 20200265916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => MEMORY AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/596368 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596368 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/596368
Memory and operation method thereof including accessing redundancy world lines by memory controller Oct 7, 2019 Issued
Array ( [id] => 16192759 [patent_doc_number] => 20200233608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/578770 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578770 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/578770
Semiconductor memory device including program operation status flag cells Sep 22, 2019 Issued
Array ( [id] => 15331027 [patent_doc_number] => 20200005843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => SEMICONDUCTOR MEMORY APPARATUS WITH A WRITE VOLTAGE LEVEL DETECTION [patent_app_type] => utility [patent_app_number] => 16/567906 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16567906 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/567906
Semiconductor memory apparatus with a write voltage level detection Sep 10, 2019 Issued
Array ( [id] => 17238361 [patent_doc_number] => 11182241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Grouping bits of a code word for memory device operations [patent_app_type] => utility [patent_app_number] => 16/551530 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 19191 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16551530 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/551530
Grouping bits of a code word for memory device operations Aug 25, 2019 Issued
Array ( [id] => 15120743 [patent_doc_number] => 20190347004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => NONVOLATILE MEMORY APPARATUS AND VERIFICATION WRITE METHOD THEREOF FOR REDUCING PROGRAM TIME [patent_app_type] => utility [patent_app_number] => 16/521235 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521235 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521235
NONVOLATILE MEMORY APPARATUS AND VERIFICATION WRITE METHOD THEREOF FOR REDUCING PROGRAM TIME Jul 23, 2019 Abandoned
Array ( [id] => 16585815 [patent_doc_number] => 20210020217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => ENCODER FOR MEMORY SYSTEM AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/517212 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517212 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517212
Encoder for memory system and method thereof Jul 18, 2019 Issued
Array ( [id] => 16440138 [patent_doc_number] => 20200357465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => DATA STORAGE MANAGEMENT [patent_app_type] => utility [patent_app_number] => 16/516900 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516900 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/516900
Data storage management in a device including removable and embedded storage areas Jul 18, 2019 Issued
Array ( [id] => 16585823 [patent_doc_number] => 20210020225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => POWERGATE BIASING TECHNIQUES FOR MEMORY APPLICATIONS [patent_app_type] => utility [patent_app_number] => 16/516094 [patent_app_country] => US [patent_app_date] => 2019-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516094 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/516094
Powergate biasing techniques for memory applications Jul 17, 2019 Issued
Array ( [id] => 16132031 [patent_doc_number] => 10699782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Nonvolatile memory device and method of operation with a word line setup time based on two sequential read voltages [patent_app_type] => utility [patent_app_number] => 16/503169 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 11042 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503169 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503169
Nonvolatile memory device and method of operation with a word line setup time based on two sequential read voltages Jul 2, 2019 Issued
Array ( [id] => 18205210 [patent_doc_number] => 11587612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Neural network memory with an array of variable resistance memory cells [patent_app_type] => utility [patent_app_number] => 16/502978 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8819 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502978 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502978
Neural network memory with an array of variable resistance memory cells Jul 2, 2019 Issued
Array ( [id] => 17925673 [patent_doc_number] => 11468932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Magnetic memory device with write current flowing simultaneously through non-adjacent lines in memory cell array [patent_app_type] => utility [patent_app_number] => 17/254592 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 11473 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17254592 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/254592
Magnetic memory device with write current flowing simultaneously through non-adjacent lines in memory cell array Jun 19, 2019 Issued
Array ( [id] => 17188550 [patent_doc_number] => 20210335435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION [patent_app_type] => utility [patent_app_number] => 16/625479 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16625479 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/625479
JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION May 30, 2019 Abandoned
Array ( [id] => 17847709 [patent_doc_number] => 11437093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Methods for mitigating power loss events during operation of memory devices and memory devices employing the same [patent_app_type] => utility [patent_app_number] => 16/418016 [patent_app_country] => US [patent_app_date] => 2019-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9048 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16418016 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/418016
Methods for mitigating power loss events during operation of memory devices and memory devices employing the same May 20, 2019 Issued
Array ( [id] => 14784391 [patent_doc_number] => 20190267093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => METHODS FOR PROGRAMMING MEMORY [patent_app_type] => utility [patent_app_number] => 16/412627 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412627 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412627
Voltage generation systems for programming memory May 14, 2019 Issued
Array ( [id] => 14784393 [patent_doc_number] => 20190267094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => METHODS FOR PROGRAMMING MEMORY [patent_app_type] => utility [patent_app_number] => 16/412661 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412661 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412661
Methods for programming memory including an overdrive voltage for gating an access line voltage May 14, 2019 Issued
Array ( [id] => 16958868 [patent_doc_number] => 11062745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => FDSOI sense amplifier configuration in a memory device [patent_app_type] => utility [patent_app_number] => 16/410231 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16410231 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/410231
FDSOI sense amplifier configuration in a memory device May 12, 2019 Issued
Array ( [id] => 16233671 [patent_doc_number] => 10741231 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-11 [patent_title] => Memory access interface device including phase and duty cycle adjusting circuits for memory access signals [patent_app_type] => utility [patent_app_number] => 16/408873 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4443 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408873 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/408873
Memory access interface device including phase and duty cycle adjusting circuits for memory access signals May 9, 2019 Issued
Array ( [id] => 16425130 [patent_doc_number] => 20200350328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => SINGLE-GATE MULTIPLE-TIME PROGRAMMING NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/401429 [patent_app_country] => US [patent_app_date] => 2019-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1664 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16401429 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/401429
SINGLE-GATE MULTIPLE-TIME PROGRAMMING NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF May 1, 2019 Abandoned
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