Search

Gary Chin

Examiner (ID: 1842)

Most Active Art Unit
2304
Art Unit(s)
2306, 2304, 2307, 3661, 2763, 3614, 2203
Total Applications
2057
Issued Applications
1788
Pending Applications
41
Abandoned Applications
228

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16417625 [patent_doc_number] => 10825525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Programming non-volatile electronic memory device with NAND architecture [patent_app_type] => utility [patent_app_number] => 16/226476 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 12686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226476 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226476
Programming non-volatile electronic memory device with NAND architecture Dec 18, 2018 Issued
Array ( [id] => 16324004 [patent_doc_number] => 10783974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Verification of an excessively high threshold voltage in a memory device [patent_app_type] => utility [patent_app_number] => 16/225253 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 11331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16225253 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/225253
Verification of an excessively high threshold voltage in a memory device Dec 18, 2018 Issued
Array ( [id] => 16080147 [patent_doc_number] => 20200194060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => GLOBAL BIT LINE LATCH PERFORMANCE AND POWER OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 16/223413 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5664 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16223413 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/223413
Global bit line latch performance and power optimization Dec 17, 2018 Issued
Array ( [id] => 15502917 [patent_doc_number] => 20200051647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => MEMORY SYSTEM WITH MEMORY REGION READ COUNTS AND A MEMORY GROUP READ COUNT AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/221956 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16221956 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/221956
Memory system with memory region read counts and a memory group read count and operating method thereof Dec 16, 2018 Issued
Array ( [id] => 16080125 [patent_doc_number] => 20200194049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => Ferroelectric Memory-Based Synapses [patent_app_type] => utility [patent_app_number] => 16/221175 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16221175 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/221175
Ferroelectric memory-based synapses Dec 13, 2018 Issued
Array ( [id] => 14220683 [patent_doc_number] => 20190122726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => ADAPTIVE READ THRESHOLD VOLTAGE TRACKING WITH GAP ESTIMATION BETWEEN ADJACENT READ THRESHOLD VOLTAGES [patent_app_type] => utility [patent_app_number] => 16/217883 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16217883 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/217883
Adaptive read threshold voltage tracking with gap estimation between adjacent read threshold voltages Dec 11, 2018 Issued
Array ( [id] => 16487423 [patent_doc_number] => 20200381032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => STORAGE CIRCUIT PROVIDED WITH VARIABLE RESISTANCE TYPE ELEMENT, AND SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 16/770411 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16770411 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/770411
Storage circuit provided with variable resistance elements, reference voltage circuit and sense amplifier Dec 9, 2018 Issued
Array ( [id] => 16021053 [patent_doc_number] => 20200185370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => Integrated Assemblies Comprising Vertically-Stacked Decks [patent_app_type] => utility [patent_app_number] => 16/213257 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16213257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/213257
Integrated assemblies comprising vertically-stacked decks of memory arrays Dec 6, 2018 Issued
Array ( [id] => 15954775 [patent_doc_number] => 10665300 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-26 [patent_title] => Apparatus and methods for discharging control gates after performing an access operation on a memory cell [patent_app_type] => utility [patent_app_number] => 16/186677 [patent_app_country] => US [patent_app_date] => 2018-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9373 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16186677 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/186677
Apparatus and methods for discharging control gates after performing an access operation on a memory cell Nov 11, 2018 Issued
Array ( [id] => 14784327 [patent_doc_number] => 20190267061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/186367 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16186367 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/186367
Memory device with two column address decoders and latches Nov 8, 2018 Issued
Array ( [id] => 14968591 [patent_doc_number] => 20190311774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/184783 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12880 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184783 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184783
Test modes for a semiconductor memory device with stacked memory chips using a chip identification Nov 7, 2018 Issued
Array ( [id] => 15791103 [patent_doc_number] => 10629281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Nonvolatile memory apparatus and an operating method thereof based on a power-up signal [patent_app_type] => utility [patent_app_number] => 16/184773 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7904 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184773 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184773
Nonvolatile memory apparatus and an operating method thereof based on a power-up signal Nov 7, 2018 Issued
Array ( [id] => 15889099 [patent_doc_number] => 10650898 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-12 [patent_title] => Erase operation in 3D NAND flash memory including pathway impedance compensation [patent_app_type] => utility [patent_app_number] => 16/182031 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 22469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16182031 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/182031
Erase operation in 3D NAND flash memory including pathway impedance compensation Nov 5, 2018 Issued
Array ( [id] => 15518897 [patent_doc_number] => 10566042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Magnetic tunnel junction devices and magnetoresistive memory devices [patent_app_type] => utility [patent_app_number] => 16/169653 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/169653
Magnetic tunnel junction devices and magnetoresistive memory devices Oct 23, 2018 Issued
Array ( [id] => 15547153 [patent_doc_number] => 10573366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Unidirectional spin torque transfer magnetic memory cell structure and methods of programming the same [patent_app_type] => utility [patent_app_number] => 16/164606 [patent_app_country] => US [patent_app_date] => 2018-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6402 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16164606 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/164606
Unidirectional spin torque transfer magnetic memory cell structure and methods of programming the same Oct 17, 2018 Issued
Array ( [id] => 15775211 [patent_doc_number] => 20200118623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => MEMRISTIVE DEVICE AND METHOD BASED ON ION MIGRATION OVER ONE OR MORE NANOWIRES [patent_app_type] => utility [patent_app_number] => 16/159075 [patent_app_country] => US [patent_app_date] => 2018-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159075 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/159075
Memristive device and method based on ion migration over one or more nanowires Oct 11, 2018 Issued
Array ( [id] => 13962789 [patent_doc_number] => 20190057739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => VARIABLE RESISTANCE MEMORY WITH LATTICE ARRAY USING ENCLOSING TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/153143 [patent_app_country] => US [patent_app_date] => 2018-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16153143 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/153143
Variable resistance memory with lattice array using enclosing transistors Oct 4, 2018 Issued
Array ( [id] => 17239341 [patent_doc_number] => 11183228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Memory circuit device including a selection circuit unit shared by a write circuit unit and a read circut unit [patent_app_type] => utility [patent_app_number] => 16/647155 [patent_app_country] => US [patent_app_date] => 2018-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 9319 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16647155 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/647155
Memory circuit device including a selection circuit unit shared by a write circuit unit and a read circut unit Sep 13, 2018 Issued
Array ( [id] => 14079555 [patent_doc_number] => 20190088665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => COMPACT EEPROM MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/130593 [patent_app_country] => US [patent_app_date] => 2018-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16130593 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/130593
Compact EEPROM memory cell with a gate dielectric layer having two different thicknesses Sep 12, 2018 Issued
Array ( [id] => 14968547 [patent_doc_number] => 20190311752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND THE METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/128803 [patent_app_country] => US [patent_app_date] => 2018-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16128803 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/128803
Semiconductor memory device for resetting counter synchronized with data clock by using reset signal synchronized with system clock and method for operating the same Sep 11, 2018 Issued
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