Gary Chin

Array ( [id] => 19539213 [patent_doc_number] => 12131768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Dynamic random access memory (DRAM) multi-wordline direct refresh management including aliasing row counter policy for row hammer mitigation [patent_app_type] => utility [patent_app_number] => 17/896337 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18097086 [patent_doc_number] => 20220415427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => APPARATUSES AND METHODS FOR TRACKING WORD LINE ACCESSES [patent_app_type] => utility [patent_app_number] => 17/822033 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19828573 [patent_doc_number] => 12249364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Apparatus with non-linear delay variations for scheduling memory refresh operations and methods for operating the same [patent_app_type] => utility [patent_app_number] => 17/890040 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5924 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17890040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19183589 [patent_doc_number] => 11990185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Dynamic word line reconfiguration for NAND structure [patent_app_type] => utility [patent_app_number] => 17/888063 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 19513 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18472726 [patent_doc_number] => 20230207014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/818833 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19720128 [patent_doc_number] => 12205671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Circuit structure and related method to compensate for sense amplifier leakage [patent_app_type] => utility [patent_app_number] => 17/815273 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4874 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18532990 [patent_doc_number] => 20230238065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/871251 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8992 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17992965 [patent_doc_number] => 20220359002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => MEMORY DEVICE INCLUDING A WORD LINE WITH PORTIONS WITH DIFFERENT SIZES IN DIFFERENT METAL LAYERS [patent_app_type] => utility [patent_app_number] => 17/871635 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19376455 [patent_doc_number] => 12068033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Memory device and method of operating the memory device including detrapping operations during programming [patent_app_type] => utility [patent_app_number] => 17/870570 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 19078 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19828803 [patent_doc_number] => 12249598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Integrated assemblies comprising vertically-stacked decks with interconnected conductive lines [patent_app_type] => utility [patent_app_number] => 17/862277 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7966 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17862277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19328618 [patent_doc_number] => 12046307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Managing program verify voltage offsets for charge coupling and lateral migration compensation in memory devices [patent_app_type] => utility [patent_app_number] => 17/860711 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 16405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19704702 [patent_doc_number] => 12198748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Semiconductor memory devices and controller including adjustable strobe delay [patent_app_type] => utility [patent_app_number] => 18/019349 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5134 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18019349 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19720090 [patent_doc_number] => 12205633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Non-volatile memory device with reference voltage circuit including column(s) of reference bit cells adjacent columns of memory bit cells within a memory cell array [patent_app_type] => utility [patent_app_number] => 17/806792 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3776 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18122643 [patent_doc_number] => 20230008246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => Memory system and memory access interface device thereof [patent_app_type] => utility [patent_app_number] => 17/830643 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17830643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17870419 [patent_doc_number] => 20220293156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SIGNAL AMPLIFICATION IN MRAM DURING READING [patent_app_type] => utility [patent_app_number] => 17/828905 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19108442 [patent_doc_number] => 11961555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Resistive memory device with boundary and edge transistors coupled to edge bit lines [patent_app_type] => utility [patent_app_number] => 17/827851 [patent_app_country] => US [patent_app_date] => 2022-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12496 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19168265 [patent_doc_number] => 11984176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Method and apparatus of testing word line to detect fault after repair [patent_app_type] => utility [patent_app_number] => 17/662895 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5624 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19153571 [patent_doc_number] => 11978492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Power supply generator assist [patent_app_type] => utility [patent_app_number] => 17/737234 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5573 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737234 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17810602 [patent_doc_number] => 20220262437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => TECHNIQUES FOR PROGRAMMING MULTI-LEVEL SELF-SELECTING MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/735598 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19341280 [patent_doc_number] => 12051475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Memory-read verification [patent_app_type] => utility [patent_app_number] => 17/721005 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721005 [rel_patent_id] =>[rel_patent_doc_number] =>)