Search

Gary Chin

Examiner (ID: 1842)

Most Active Art Unit
2304
Art Unit(s)
2306, 2304, 2307, 3661, 2763, 3614, 2203
Total Applications
2057
Issued Applications
1788
Pending Applications
41
Abandoned Applications
228

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17144975 [patent_doc_number] => 20210312988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => VARIABLE RESISTANCE MEMORY WITH LATTICE ARRAY USING ENCLOSING TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/348194 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17348194 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/348194
Variable resistance memory with lattice array using enclosing transistors Jun 14, 2021 Issued
Array ( [id] => 17157771 [patent_doc_number] => 20210318822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => MEMORY SUB-SYSTEM TEMPERATURE REGULATION [patent_app_type] => utility [patent_app_number] => 17/345785 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345785 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345785
Memory sub-system temperature regulation by modifying a data parameter Jun 10, 2021 Issued
Array ( [id] => 18039708 [patent_doc_number] => 20220383925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => MEMORY READ CIRCUITRY WITH A FLIPPED VOLTAGE FOLLOWER [patent_app_type] => utility [patent_app_number] => 17/333109 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333109 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333109
Memory read circuitry with a flipped voltage follower May 27, 2021 Issued
Array ( [id] => 17810613 [patent_doc_number] => 20220262448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => MEMORY DEVICE AND MEMORY SYSTEM FOR EXECUTING A TEST [patent_app_type] => utility [patent_app_number] => 17/313494 [patent_app_country] => US [patent_app_date] => 2021-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313494 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/313494
Memory device and memory system controlling generation of data strobe signal based on executing a test May 5, 2021 Issued
Array ( [id] => 18562753 [patent_doc_number] => 11728003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => System and memory with configurable error-correction code (ECC) data protection and related methods [patent_app_type] => utility [patent_app_number] => 17/245981 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 23327 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245981 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/245981
System and memory with configurable error-correction code (ECC) data protection and related methods Apr 29, 2021 Issued
Array ( [id] => 17985757 [patent_doc_number] => 20220351794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => ANALOG CONTENT ADDRESSABLE MEMORY WITH ANALOG INPUT AND ANALOG OUTPUT [patent_app_type] => utility [patent_app_number] => 17/245540 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245540 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/245540
Analog content addressable memory with analog input and analog output Apr 29, 2021 Issued
Array ( [id] => 17025190 [patent_doc_number] => 20210249062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => METHOD FOR ENHANCING TUNNEL MAGNETORESISTANCE IN MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/243612 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17243612 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/243612
Method for enhancing tunnel magnetoresistance in memory device Apr 28, 2021 Issued
Array ( [id] => 17188555 [patent_doc_number] => 20210335440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => MEMORY TEST ENGINE WITH FULLY PROGRAMMABLE PATTERNS [patent_app_type] => utility [patent_app_number] => 17/243304 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17243304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/243304
MEMORY TEST ENGINE WITH FULLY PROGRAMMABLE PATTERNS Apr 27, 2021 Abandoned
Array ( [id] => 19137817 [patent_doc_number] => 11972788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Apparatuses, systems, and methods for controller directed targeted refresh operations based on sampling command [patent_app_type] => utility [patent_app_number] => 17/301970 [patent_app_country] => US [patent_app_date] => 2021-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10004 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301970
Apparatuses, systems, and methods for controller directed targeted refresh operations based on sampling command Apr 19, 2021 Issued
Array ( [id] => 18464181 [patent_doc_number] => 11688474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Dual verify for quick charge loss reduction in memory cells [patent_app_type] => utility [patent_app_number] => 17/234502 [patent_app_country] => US [patent_app_date] => 2021-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 13853 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234502 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/234502
Dual verify for quick charge loss reduction in memory cells Apr 18, 2021 Issued
Array ( [id] => 17144966 [patent_doc_number] => 20210312979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => Read Circuitry for Resistive Change Memories [patent_app_type] => utility [patent_app_number] => 17/218373 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218373 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/218373
Read Circuitry for Resistive Change Memories Mar 30, 2021 Abandoned
Array ( [id] => 17463436 [patent_doc_number] => 20220076742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => RESISTIVE MEMORY DEVICE AND METHOD FOR READING DATA IN THE RESISTIVE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/214078 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214078 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214078
Resistive memory device and method for reading data in the resistive memory device Mar 25, 2021 Issued
Array ( [id] => 17886170 [patent_doc_number] => 20220301647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => MEMORY WITH ONE-TIME PROGRAMMABLE (OTP) CELLS [patent_app_type] => utility [patent_app_number] => 17/249906 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17249906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/249906
Memory with one-time programmable (OTP) cells and reading operations thereof Mar 17, 2021 Issued
Array ( [id] => 18088373 [patent_doc_number] => 11538512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Memory device that executes a read operation based on a self-reference scheme [patent_app_type] => utility [patent_app_number] => 17/200966 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 23028 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200966 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200966
Memory device that executes a read operation based on a self-reference scheme Mar 14, 2021 Issued
Array ( [id] => 17085253 [patent_doc_number] => 20210280260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/187699 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187699 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187699
Semiconductor memory device with erase verification on memory strings in a memory block Feb 25, 2021 Issued
Array ( [id] => 17463467 [patent_doc_number] => 20220076773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/187705 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187705 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187705
Memory system including parities written to dummy memory cell groups Feb 25, 2021 Issued
Array ( [id] => 18593126 [patent_doc_number] => 11742035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Memory device including bit line precharge operation during program verify operation [patent_app_type] => utility [patent_app_number] => 17/183955 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 10625 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17183955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/183955
Memory device including bit line precharge operation during program verify operation Feb 23, 2021 Issued
Array ( [id] => 16888693 [patent_doc_number] => 20210174890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => TEST CIRCUIT AND MEMORY CHIP USING TEST CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/182242 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/182242
TEST CIRCUIT AND MEMORY CHIP USING TEST CIRCUIT Feb 22, 2021 Abandoned
Array ( [id] => 18804850 [patent_doc_number] => 11838020 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-05 [patent_title] => Semiconductor memory device including write driver with power gating structures and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/179615 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 11326 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179615 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179615
Semiconductor memory device including write driver with power gating structures and operating method thereof Feb 18, 2021 Issued
Array ( [id] => 16873300 [patent_doc_number] => 20210166767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => METHODS AND APPARATUS FOR PROGRAMMING MEMORY [patent_app_type] => utility [patent_app_number] => 17/176345 [patent_app_country] => US [patent_app_date] => 2021-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17176345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/176345
Adjusting voltage levels applied to a control gate of a string driver in a memory Feb 15, 2021 Issued
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